251 lines
6.6 KiB
C
251 lines
6.6 KiB
C
#include <linux/linkage.h>
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/kprobes.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/sysdev.h>
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#include <linux/bitops.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <asm/atomic.h>
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#include <asm/system.h>
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#include <asm/timer.h>
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#include <asm/hw_irq.h>
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#include <asm/pgtable.h>
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#include <asm/desc.h>
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#include <asm/apic.h>
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#include <asm/setup.h>
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#include <asm/i8259.h>
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#include <asm/traps.h>
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/*
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* ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
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* (these are usually mapped to vectors 0x30-0x3f)
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*/
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/*
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* The IO-APIC gives us many more interrupt sources. Most of these
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* are unused but an SMP system is supposed to have enough memory ...
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* sometimes (mostly wrt. hw bugs) we get corrupted vectors all
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* across the spectrum, so we really want to be prepared to get all
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* of these. Plus, more powerful systems might have more than 64
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* IO-APIC registers.
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*
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* (these are usually mapped into the 0x30-0xff vector range)
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*/
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#ifdef CONFIG_X86_32
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/*
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* Note that on a 486, we don't want to do a SIGFPE on an irq13
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* as the irq is unreliable, and exception 16 works correctly
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* (ie as explained in the intel literature). On a 386, you
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* can't use exception 16 due to bad IBM design, so we have to
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* rely on the less exact irq13.
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*
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* Careful.. Not only is IRQ13 unreliable, but it is also
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* leads to races. IBM designers who came up with it should
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* be shot.
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*/
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static irqreturn_t math_error_irq(int cpl, void *dev_id)
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{
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outb(0, 0xF0);
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if (ignore_fpu_irq || !boot_cpu_data.hard_math)
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return IRQ_NONE;
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math_error((void __user *)get_irq_regs()->ip);
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return IRQ_HANDLED;
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}
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/*
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* New motherboards sometimes make IRQ 13 be a PCI interrupt,
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* so allow interrupt sharing.
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*/
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static struct irqaction fpu_irq = {
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.handler = math_error_irq,
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.name = "fpu",
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};
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#endif
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/*
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* IRQ2 is cascade interrupt to second interrupt controller
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*/
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static struct irqaction irq2 = {
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.handler = no_action,
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.name = "cascade",
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};
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DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
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[0 ... NR_VECTORS - 1] = -1,
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};
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int vector_used_by_percpu_irq(unsigned int vector)
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{
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int cpu;
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for_each_online_cpu(cpu) {
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if (per_cpu(vector_irq, cpu)[vector] != -1)
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return 1;
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}
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return 0;
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}
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/* Number of legacy interrupts */
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int nr_legacy_irqs __read_mostly = NR_IRQS_LEGACY;
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void __init init_ISA_irqs(void)
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{
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int i;
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#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
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init_bsp_APIC();
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#endif
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legacy_pic->init(0);
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/*
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* 16 old-style INTA-cycle interrupts:
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*/
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for (i = 0; i < NR_IRQS_LEGACY; i++) {
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struct irq_desc *desc = irq_to_desc(i);
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desc->status = IRQ_DISABLED;
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desc->action = NULL;
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desc->depth = 1;
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set_irq_chip_and_handler_name(i, &i8259A_chip,
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handle_level_irq, "XT");
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}
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}
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void __init init_IRQ(void)
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{
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int i;
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/*
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* On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
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* If these IRQ's are handled by legacy interrupt-controllers like PIC,
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* then this configuration will likely be static after the boot. If
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* these IRQ's are handled by more mordern controllers like IO-APIC,
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* then this vector space can be freed and re-used dynamically as the
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* irq's migrate etc.
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*/
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for (i = 0; i < nr_legacy_irqs; i++)
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per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i;
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x86_init.irqs.intr_init();
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}
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static void __init smp_intr_init(void)
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{
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#ifdef CONFIG_SMP
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#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
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/*
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* The reschedule interrupt is a CPU-to-CPU reschedule-helper
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* IPI, driven by wakeup.
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*/
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alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
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/* IPIs for invalidation */
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
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/* IPI for generic function call */
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alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
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/* IPI for generic single function call */
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alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
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call_function_single_interrupt);
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/* Low priority IPI to cleanup after moving an irq */
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set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
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set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
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/* IPI used for rebooting/stopping */
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alloc_intr_gate(REBOOT_VECTOR, reboot_interrupt);
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#endif
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#endif /* CONFIG_SMP */
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}
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static void __init apic_intr_init(void)
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{
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smp_intr_init();
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#ifdef CONFIG_X86_THERMAL_VECTOR
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alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
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#endif
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#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_LOCAL_APIC)
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alloc_intr_gate(MCE_SELF_VECTOR, mce_self_interrupt);
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#endif
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#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
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/* self generated IPI for local APIC timer */
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alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
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/* IPI for X86 platform specific use */
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alloc_intr_gate(X86_PLATFORM_IPI_VECTOR, x86_platform_ipi);
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/* IPI vectors for APIC spurious and error interrupts */
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alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
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alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
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/* Performance monitoring interrupts: */
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# ifdef CONFIG_PERF_EVENTS
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alloc_intr_gate(LOCAL_PENDING_VECTOR, perf_pending_interrupt);
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# endif
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#endif
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}
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void __init native_init_IRQ(void)
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{
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int i;
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/* Execute any quirks before the call gates are initialised: */
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x86_init.irqs.pre_vector_init();
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apic_intr_init();
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/*
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* Cover the whole vector space, no vector can escape
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* us. (some of these will be overridden and become
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* 'special' SMP interrupts)
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*/
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for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
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/* IA32_SYSCALL_VECTOR could be used in trap_init already. */
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if (!test_bit(i, used_vectors))
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set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
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}
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if (!acpi_ioapic)
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setup_irq(2, &irq2);
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#ifdef CONFIG_X86_32
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/*
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* External FPU? Set up irq13 if so, for
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* original braindamaged IBM FERR coupling.
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*/
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if (boot_cpu_data.hard_math && !cpu_has_fpu)
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setup_irq(FPU_IRQ, &fpu_irq);
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irq_ctx_init(smp_processor_id());
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#endif
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}
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