5296b56d1b
i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
56 lines
1.4 KiB
C
56 lines
1.4 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MXC_IRQS_H__
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#define __ASM_ARCH_MXC_IRQS_H__
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/*
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* So far all i.MX SoCs have 64 internal interrupts
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*/
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#define MXC_INTERNAL_IRQS 64
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#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
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#if defined CONFIG_ARCH_MX1
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#define MXC_GPIO_IRQS (32 * 4)
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#elif defined CONFIG_ARCH_MX2
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#define MXC_GPIO_IRQS (32 * 6)
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#elif defined CONFIG_ARCH_MX3
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#define MXC_GPIO_IRQS (32 * 3)
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#endif
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/*
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* The next 16 interrupts are for board specific purposes. Since
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* the kernel can only run on one machine at a time, we can re-use
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* these. If you need more, increase MXC_BOARD_IRQS, but keep it
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* within sensible limits.
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*/
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#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
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#define MXC_BOARD_IRQS 16
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#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
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#ifdef CONFIG_MX3_IPU_IRQS
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#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
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#else
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#define MX3_IPU_IRQS 0
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#endif
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#define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
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extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);
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/* all normal IRQs can be FIQs */
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#define FIQ_START 0
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/* switch betwean IRQ and FIQ */
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extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
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#endif /* __ASM_ARCH_MXC_IRQS_H__ */
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