785b6f977a
The vast majority of bit constants in this driver are defined in the header file, but TX and RX status word bits are not. This patch (which should make no functional change) defines these, to make the driver slightly more readable. Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com> Signed-off-by: David S. Miller <davem@davemloft.net>
398 lines
12 KiB
C
398 lines
12 KiB
C
/***************************************************************************
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*
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* Copyright (C) 2004-2008 SMSC
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* Copyright (C) 2005-2008 ARM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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***************************************************************************/
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#ifndef __SMSC911X_H__
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#define __SMSC911X_H__
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#define TX_FIFO_LOW_THRESHOLD ((u32)1600)
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#define SMSC911X_EEPROM_SIZE ((u32)7)
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#define USE_DEBUG 0
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/* This is the maximum number of packets to be received every
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* NAPI poll */
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#define SMSC_NAPI_WEIGHT 16
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/* implements a PHY loopback test at initialisation time, to ensure a packet
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* can be succesfully looped back */
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#define USE_PHY_WORK_AROUND
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#define DPRINTK(nlevel, klevel, fmt, args...) \
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((void)((NETIF_MSG_##nlevel & pdata->msg_enable) && \
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printk(KERN_##klevel "%s: %s: " fmt "\n", \
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pdata->dev->name, __func__, ## args)))
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#if USE_DEBUG >= 1
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#define SMSC_WARNING(nlevel, fmt, args...) \
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DPRINTK(nlevel, WARNING, fmt, ## args)
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#else
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#define SMSC_WARNING(nlevel, fmt, args...) \
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({ do {} while (0); 0; })
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#endif
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#if USE_DEBUG >= 2
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#define SMSC_TRACE(nlevel, fmt, args...) \
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DPRINTK(nlevel, INFO, fmt, ## args)
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#else
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#define SMSC_TRACE(nlevel, fmt, args...) \
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({ do {} while (0); 0; })
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#endif
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#ifdef CONFIG_DEBUG_SPINLOCK
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#define SMSC_ASSERT_MAC_LOCK(pdata) \
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WARN_ON(!spin_is_locked(&pdata->mac_lock))
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#else
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#define SMSC_ASSERT_MAC_LOCK(pdata) do {} while (0)
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#endif /* CONFIG_DEBUG_SPINLOCK */
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/* SMSC911x registers and bitfields */
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#define RX_DATA_FIFO 0x00
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#define TX_DATA_FIFO 0x20
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#define TX_CMD_A_ON_COMP_ 0x80000000
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#define TX_CMD_A_BUF_END_ALGN_ 0x03000000
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#define TX_CMD_A_4_BYTE_ALGN_ 0x00000000
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#define TX_CMD_A_16_BYTE_ALGN_ 0x01000000
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#define TX_CMD_A_32_BYTE_ALGN_ 0x02000000
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#define TX_CMD_A_DATA_OFFSET_ 0x001F0000
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#define TX_CMD_A_FIRST_SEG_ 0x00002000
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#define TX_CMD_A_LAST_SEG_ 0x00001000
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#define TX_CMD_A_BUF_SIZE_ 0x000007FF
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#define TX_CMD_B_PKT_TAG_ 0xFFFF0000
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#define TX_CMD_B_ADD_CRC_DISABLE_ 0x00002000
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#define TX_CMD_B_DISABLE_PADDING_ 0x00001000
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#define TX_CMD_B_PKT_BYTE_LENGTH_ 0x000007FF
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#define RX_STATUS_FIFO 0x40
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#define RX_STS_ES_ 0x00008000
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#define RX_STS_LENGTH_ERR_ 0x00001000
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#define RX_STS_MCAST_ 0x00000400
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#define RX_STS_FRAME_TYPE_ 0x00000020
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#define RX_STS_CRC_ERR_ 0x00000002
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#define RX_STATUS_FIFO_PEEK 0x44
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#define TX_STATUS_FIFO 0x48
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#define TX_STS_ES_ 0x00008000
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#define TX_STS_LOST_CARRIER_ 0x00000800
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#define TX_STS_NO_CARRIER_ 0x00000400
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#define TX_STS_LATE_COL_ 0x00000200
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#define TX_STS_EXCESS_COL_ 0x00000100
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#define TX_STATUS_FIFO_PEEK 0x4C
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#define ID_REV 0x50
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#define ID_REV_CHIP_ID_ 0xFFFF0000
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#define ID_REV_REV_ID_ 0x0000FFFF
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#define INT_CFG 0x54
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#define INT_CFG_INT_DEAS_ 0xFF000000
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#define INT_CFG_INT_DEAS_CLR_ 0x00004000
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#define INT_CFG_INT_DEAS_STS_ 0x00002000
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#define INT_CFG_IRQ_INT_ 0x00001000
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#define INT_CFG_IRQ_EN_ 0x00000100
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#define INT_CFG_IRQ_POL_ 0x00000010
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#define INT_CFG_IRQ_TYPE_ 0x00000001
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#define INT_STS 0x58
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#define INT_STS_SW_INT_ 0x80000000
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#define INT_STS_TXSTOP_INT_ 0x02000000
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#define INT_STS_RXSTOP_INT_ 0x01000000
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#define INT_STS_RXDFH_INT_ 0x00800000
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#define INT_STS_RXDF_INT_ 0x00400000
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#define INT_STS_TX_IOC_ 0x00200000
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#define INT_STS_RXD_INT_ 0x00100000
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#define INT_STS_GPT_INT_ 0x00080000
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#define INT_STS_PHY_INT_ 0x00040000
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#define INT_STS_PME_INT_ 0x00020000
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#define INT_STS_TXSO_ 0x00010000
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#define INT_STS_RWT_ 0x00008000
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#define INT_STS_RXE_ 0x00004000
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#define INT_STS_TXE_ 0x00002000
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#define INT_STS_TDFU_ 0x00000800
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#define INT_STS_TDFO_ 0x00000400
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#define INT_STS_TDFA_ 0x00000200
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#define INT_STS_TSFF_ 0x00000100
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#define INT_STS_TSFL_ 0x00000080
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#define INT_STS_RXDF_ 0x00000040
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#define INT_STS_RDFL_ 0x00000020
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#define INT_STS_RSFF_ 0x00000010
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#define INT_STS_RSFL_ 0x00000008
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#define INT_STS_GPIO2_INT_ 0x00000004
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#define INT_STS_GPIO1_INT_ 0x00000002
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#define INT_STS_GPIO0_INT_ 0x00000001
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#define INT_EN 0x5C
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#define INT_EN_SW_INT_EN_ 0x80000000
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#define INT_EN_TXSTOP_INT_EN_ 0x02000000
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#define INT_EN_RXSTOP_INT_EN_ 0x01000000
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#define INT_EN_RXDFH_INT_EN_ 0x00800000
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#define INT_EN_TIOC_INT_EN_ 0x00200000
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#define INT_EN_RXD_INT_EN_ 0x00100000
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#define INT_EN_GPT_INT_EN_ 0x00080000
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#define INT_EN_PHY_INT_EN_ 0x00040000
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#define INT_EN_PME_INT_EN_ 0x00020000
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#define INT_EN_TXSO_EN_ 0x00010000
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#define INT_EN_RWT_EN_ 0x00008000
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#define INT_EN_RXE_EN_ 0x00004000
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#define INT_EN_TXE_EN_ 0x00002000
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#define INT_EN_TDFU_EN_ 0x00000800
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#define INT_EN_TDFO_EN_ 0x00000400
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#define INT_EN_TDFA_EN_ 0x00000200
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#define INT_EN_TSFF_EN_ 0x00000100
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#define INT_EN_TSFL_EN_ 0x00000080
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#define INT_EN_RXDF_EN_ 0x00000040
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#define INT_EN_RDFL_EN_ 0x00000020
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#define INT_EN_RSFF_EN_ 0x00000010
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#define INT_EN_RSFL_EN_ 0x00000008
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#define INT_EN_GPIO2_INT_ 0x00000004
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#define INT_EN_GPIO1_INT_ 0x00000002
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#define INT_EN_GPIO0_INT_ 0x00000001
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#define BYTE_TEST 0x64
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#define FIFO_INT 0x68
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#define FIFO_INT_TX_AVAIL_LEVEL_ 0xFF000000
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#define FIFO_INT_TX_STS_LEVEL_ 0x00FF0000
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#define FIFO_INT_RX_AVAIL_LEVEL_ 0x0000FF00
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#define FIFO_INT_RX_STS_LEVEL_ 0x000000FF
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#define RX_CFG 0x6C
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#define RX_CFG_RX_END_ALGN_ 0xC0000000
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#define RX_CFG_RX_END_ALGN4_ 0x00000000
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#define RX_CFG_RX_END_ALGN16_ 0x40000000
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#define RX_CFG_RX_END_ALGN32_ 0x80000000
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#define RX_CFG_RX_DMA_CNT_ 0x0FFF0000
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#define RX_CFG_RX_DUMP_ 0x00008000
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#define RX_CFG_RXDOFF_ 0x00001F00
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#define TX_CFG 0x70
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#define TX_CFG_TXS_DUMP_ 0x00008000
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#define TX_CFG_TXD_DUMP_ 0x00004000
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#define TX_CFG_TXSAO_ 0x00000004
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#define TX_CFG_TX_ON_ 0x00000002
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#define TX_CFG_STOP_TX_ 0x00000001
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#define HW_CFG 0x74
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#define HW_CFG_TTM_ 0x00200000
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#define HW_CFG_SF_ 0x00100000
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#define HW_CFG_TX_FIF_SZ_ 0x000F0000
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#define HW_CFG_TR_ 0x00003000
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#define HW_CFG_SRST_ 0x00000001
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/* only available on 115/117 */
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#define HW_CFG_PHY_CLK_SEL_ 0x00000060
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#define HW_CFG_PHY_CLK_SEL_INT_PHY_ 0x00000000
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#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ 0x00000020
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#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ 0x00000040
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#define HW_CFG_SMI_SEL_ 0x00000010
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#define HW_CFG_EXT_PHY_DET_ 0x00000008
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#define HW_CFG_EXT_PHY_EN_ 0x00000004
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#define HW_CFG_SRST_TO_ 0x00000002
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/* only available on 116/118 */
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#define HW_CFG_32_16_BIT_MODE_ 0x00000004
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#define RX_DP_CTRL 0x78
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#define RX_DP_CTRL_RX_FFWD_ 0x80000000
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#define RX_FIFO_INF 0x7C
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#define RX_FIFO_INF_RXSUSED_ 0x00FF0000
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#define RX_FIFO_INF_RXDUSED_ 0x0000FFFF
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#define TX_FIFO_INF 0x80
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#define TX_FIFO_INF_TSUSED_ 0x00FF0000
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#define TX_FIFO_INF_TDFREE_ 0x0000FFFF
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#define PMT_CTRL 0x84
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#define PMT_CTRL_PM_MODE_ 0x00003000
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#define PMT_CTRL_PM_MODE_D0_ 0x00000000
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#define PMT_CTRL_PM_MODE_D1_ 0x00001000
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#define PMT_CTRL_PM_MODE_D2_ 0x00002000
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#define PMT_CTRL_PM_MODE_D3_ 0x00003000
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#define PMT_CTRL_PHY_RST_ 0x00000400
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#define PMT_CTRL_WOL_EN_ 0x00000200
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#define PMT_CTRL_ED_EN_ 0x00000100
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#define PMT_CTRL_PME_TYPE_ 0x00000040
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#define PMT_CTRL_WUPS_ 0x00000030
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#define PMT_CTRL_WUPS_NOWAKE_ 0x00000000
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#define PMT_CTRL_WUPS_ED_ 0x00000010
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#define PMT_CTRL_WUPS_WOL_ 0x00000020
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#define PMT_CTRL_WUPS_MULTI_ 0x00000030
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#define PMT_CTRL_PME_IND_ 0x00000008
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#define PMT_CTRL_PME_POL_ 0x00000004
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#define PMT_CTRL_PME_EN_ 0x00000002
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#define PMT_CTRL_READY_ 0x00000001
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#define GPIO_CFG 0x88
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#define GPIO_CFG_LED3_EN_ 0x40000000
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#define GPIO_CFG_LED2_EN_ 0x20000000
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#define GPIO_CFG_LED1_EN_ 0x10000000
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#define GPIO_CFG_GPIO2_INT_POL_ 0x04000000
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#define GPIO_CFG_GPIO1_INT_POL_ 0x02000000
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#define GPIO_CFG_GPIO0_INT_POL_ 0x01000000
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#define GPIO_CFG_EEPR_EN_ 0x00700000
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#define GPIO_CFG_GPIOBUF2_ 0x00040000
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#define GPIO_CFG_GPIOBUF1_ 0x00020000
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#define GPIO_CFG_GPIOBUF0_ 0x00010000
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#define GPIO_CFG_GPIODIR2_ 0x00000400
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#define GPIO_CFG_GPIODIR1_ 0x00000200
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#define GPIO_CFG_GPIODIR0_ 0x00000100
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#define GPIO_CFG_GPIOD4_ 0x00000020
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#define GPIO_CFG_GPIOD3_ 0x00000010
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#define GPIO_CFG_GPIOD2_ 0x00000004
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#define GPIO_CFG_GPIOD1_ 0x00000002
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#define GPIO_CFG_GPIOD0_ 0x00000001
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#define GPT_CFG 0x8C
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#define GPT_CFG_TIMER_EN_ 0x20000000
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#define GPT_CFG_GPT_LOAD_ 0x0000FFFF
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#define GPT_CNT 0x90
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#define GPT_CNT_GPT_CNT_ 0x0000FFFF
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#define WORD_SWAP 0x98
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#define FREE_RUN 0x9C
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#define RX_DROP 0xA0
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#define MAC_CSR_CMD 0xA4
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#define MAC_CSR_CMD_CSR_BUSY_ 0x80000000
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#define MAC_CSR_CMD_R_NOT_W_ 0x40000000
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#define MAC_CSR_CMD_CSR_ADDR_ 0x000000FF
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#define MAC_CSR_DATA 0xA8
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#define AFC_CFG 0xAC
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#define AFC_CFG_AFC_HI_ 0x00FF0000
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#define AFC_CFG_AFC_LO_ 0x0000FF00
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#define AFC_CFG_BACK_DUR_ 0x000000F0
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#define AFC_CFG_FCMULT_ 0x00000008
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#define AFC_CFG_FCBRD_ 0x00000004
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#define AFC_CFG_FCADD_ 0x00000002
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#define AFC_CFG_FCANY_ 0x00000001
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#define E2P_CMD 0xB0
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#define E2P_CMD_EPC_BUSY_ 0x80000000
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#define E2P_CMD_EPC_CMD_ 0x70000000
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#define E2P_CMD_EPC_CMD_READ_ 0x00000000
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#define E2P_CMD_EPC_CMD_EWDS_ 0x10000000
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#define E2P_CMD_EPC_CMD_EWEN_ 0x20000000
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#define E2P_CMD_EPC_CMD_WRITE_ 0x30000000
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#define E2P_CMD_EPC_CMD_WRAL_ 0x40000000
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#define E2P_CMD_EPC_CMD_ERASE_ 0x50000000
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#define E2P_CMD_EPC_CMD_ERAL_ 0x60000000
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#define E2P_CMD_EPC_CMD_RELOAD_ 0x70000000
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#define E2P_CMD_EPC_TIMEOUT_ 0x00000200
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#define E2P_CMD_MAC_ADDR_LOADED_ 0x00000100
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#define E2P_CMD_EPC_ADDR_ 0x000000FF
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#define E2P_DATA 0xB4
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#define E2P_DATA_EEPROM_DATA_ 0x000000FF
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#define LAN_REGISTER_EXTENT 0x00000100
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/*
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* MAC Control and Status Register (Indirect Address)
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* Offset (through the MAC_CSR CMD and DATA port)
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*/
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#define MAC_CR 0x01
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#define MAC_CR_RXALL_ 0x80000000
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#define MAC_CR_HBDIS_ 0x10000000
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#define MAC_CR_RCVOWN_ 0x00800000
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#define MAC_CR_LOOPBK_ 0x00200000
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#define MAC_CR_FDPX_ 0x00100000
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#define MAC_CR_MCPAS_ 0x00080000
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#define MAC_CR_PRMS_ 0x00040000
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#define MAC_CR_INVFILT_ 0x00020000
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#define MAC_CR_PASSBAD_ 0x00010000
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#define MAC_CR_HFILT_ 0x00008000
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#define MAC_CR_HPFILT_ 0x00002000
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#define MAC_CR_LCOLL_ 0x00001000
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#define MAC_CR_BCAST_ 0x00000800
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#define MAC_CR_DISRTY_ 0x00000400
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#define MAC_CR_PADSTR_ 0x00000100
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#define MAC_CR_BOLMT_MASK_ 0x000000C0
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#define MAC_CR_DFCHK_ 0x00000020
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#define MAC_CR_TXEN_ 0x00000008
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#define MAC_CR_RXEN_ 0x00000004
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#define ADDRH 0x02
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#define ADDRL 0x03
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#define HASHH 0x04
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#define HASHL 0x05
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#define MII_ACC 0x06
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#define MII_ACC_PHY_ADDR_ 0x0000F800
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#define MII_ACC_MIIRINDA_ 0x000007C0
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#define MII_ACC_MII_WRITE_ 0x00000002
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#define MII_ACC_MII_BUSY_ 0x00000001
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#define MII_DATA 0x07
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#define FLOW 0x08
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#define FLOW_FCPT_ 0xFFFF0000
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#define FLOW_FCPASS_ 0x00000004
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#define FLOW_FCEN_ 0x00000002
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#define FLOW_FCBSY_ 0x00000001
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#define VLAN1 0x09
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#define VLAN2 0x0A
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#define WUFF 0x0B
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#define WUCSR 0x0C
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#define WUCSR_GUE_ 0x00000200
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#define WUCSR_WUFR_ 0x00000040
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#define WUCSR_MPR_ 0x00000020
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#define WUCSR_WAKE_EN_ 0x00000004
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#define WUCSR_MPEN_ 0x00000002
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/*
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* Phy definitions (vendor-specific)
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*/
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#define LAN9118_PHY_ID 0x00C0001C
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#define MII_INTSTS 0x1D
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#define MII_INTMSK 0x1E
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#define PHY_INTMSK_AN_RCV_ (1 << 1)
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#define PHY_INTMSK_PDFAULT_ (1 << 2)
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#define PHY_INTMSK_AN_ACK_ (1 << 3)
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#define PHY_INTMSK_LNKDOWN_ (1 << 4)
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#define PHY_INTMSK_RFAULT_ (1 << 5)
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#define PHY_INTMSK_AN_COMP_ (1 << 6)
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#define PHY_INTMSK_ENERGYON_ (1 << 7)
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#define PHY_INTMSK_DEFAULT_ (PHY_INTMSK_ENERGYON_ | \
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PHY_INTMSK_AN_COMP_ | \
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PHY_INTMSK_RFAULT_ | \
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PHY_INTMSK_LNKDOWN_)
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#define ADVERTISE_PAUSE_ALL (ADVERTISE_PAUSE_CAP | \
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ADVERTISE_PAUSE_ASYM)
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#define LPA_PAUSE_ALL (LPA_PAUSE_CAP | \
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LPA_PAUSE_ASYM)
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#endif /* __SMSC911X_H__ */
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