3b1d4ed535
For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
313 lines
8.0 KiB
C
313 lines
8.0 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Setting up the clock on the MIPS boards.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/mc146818rtc.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/hardirq.h>
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#include <asm/irq.h>
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#include <asm/div64.h>
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#include <asm/cpu.h>
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#include <asm/time.h>
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#include <asm/mc146818-time.h>
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#include <asm/msc01_ic.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/prom.h>
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#ifdef CONFIG_MIPS_ATLAS
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#include <asm/mips-boards/atlasint.h>
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#endif
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#ifdef CONFIG_MIPS_MALTA
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#include <asm/mips-boards/maltaint.h>
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#endif
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#ifdef CONFIG_MIPS_SEAD
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#include <asm/mips-boards/seadint.h>
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#endif
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unsigned long cpu_khz;
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static int mips_cpu_timer_irq;
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extern int cp0_perfcount_irq;
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extern void smtc_timer_broadcast(int);
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static void mips_timer_dispatch(void)
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{
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do_IRQ(mips_cpu_timer_irq);
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}
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static void mips_perf_dispatch(void)
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{
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do_IRQ(cp0_perfcount_irq);
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}
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/*
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* Redeclare until I get around mopping the timer code insanity on MIPS.
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*/
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extern int null_perf_irq(void);
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extern int (*perf_irq)(void);
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/*
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* Possibly handle a performance counter interrupt.
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* Return true if the timer interrupt should not be checked
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*/
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static inline int handle_perf_irq (int r2)
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{
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/*
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* The performance counter overflow interrupt may be shared with the
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* timer interrupt (cp0_perfcount_irq < 0). If it is and a
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* performance counter has overflowed (perf_irq() == IRQ_HANDLED)
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* and we can't reliably determine if a counter interrupt has also
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* happened (!r2) then don't check for a timer interrupt.
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*/
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return (cp0_perfcount_irq < 0) &&
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perf_irq() == IRQ_HANDLED &&
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!r2;
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}
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irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
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{
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int cpu = smp_processor_id();
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* In an SMTC system, one Count/Compare set exists per VPE.
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* Which TC within a VPE gets the interrupt is essentially
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* random - we only know that it shouldn't be one with
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* IXMT set. Whichever TC gets the interrupt needs to
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* send special interprocessor interrupts to the other
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* TCs to make sure that they schedule, etc.
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*
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* That code is specific to the SMTC kernel, not to
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* the a particular platform, so it's invoked from
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* the general MIPS timer_interrupt routine.
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*/
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/*
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* We could be here due to timer interrupt,
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* perf counter overflow, or both.
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*/
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(void) handle_perf_irq(1);
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if (read_c0_cause() & (1 << 30)) {
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/*
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* There are things we only want to do once per tick
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* in an "MP" system. One TC of each VPE will take
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* the actual timer interrupt. The others will get
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* timer broadcast IPIs. We use whoever it is that takes
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* the tick on VPE 0 to run the full timer_interrupt().
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*/
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if (cpu_data[cpu].vpe_id == 0) {
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timer_interrupt(irq, NULL);
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} else {
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write_c0_compare(read_c0_count() +
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(mips_hpt_frequency/HZ));
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local_timer_interrupt(irq, dev_id);
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}
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smtc_timer_broadcast(cpu_data[cpu].vpe_id);
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}
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#else /* CONFIG_MIPS_MT_SMTC */
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int r2 = cpu_has_mips_r2;
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if (handle_perf_irq(r2))
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goto out;
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if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
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goto out;
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if (cpu == 0) {
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/*
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* CPU 0 handles the global timer interrupt job and process
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* accounting resets count/compare registers to trigger next
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* timer int.
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*/
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timer_interrupt(irq, NULL);
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} else {
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/* Everyone else needs to reset the timer int here as
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ll_local_timer_interrupt doesn't */
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/*
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* FIXME: need to cope with counter underflow.
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* More support needs to be added to kernel/time for
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* counter/timer interrupts on multiple CPU's
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*/
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write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
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/*
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* Other CPUs should do profiling and process accounting
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*/
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local_timer_interrupt(irq, dev_id);
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}
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out:
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#endif /* CONFIG_MIPS_MT_SMTC */
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return IRQ_HANDLED;
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}
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/*
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* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
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*/
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static unsigned int __init estimate_cpu_frequency(void)
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{
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unsigned int prid = read_c0_prid() & 0xffff00;
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unsigned int count;
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#if defined(CONFIG_MIPS_SEAD) || defined(CONFIG_MIPS_SIM)
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/*
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* The SEAD board doesn't have a real time clock, so we can't
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* really calculate the timer frequency
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* For now we hardwire the SEAD board frequency to 12MHz.
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*/
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if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
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(prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
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count = 12000000;
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else
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count = 6000000;
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#endif
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#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
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unsigned long flags;
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unsigned int start;
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local_irq_save(flags);
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/* Start counter exactly on falling edge of update flag */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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/* Start r4k counter. */
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start = read_c0_count();
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/* Read counter exactly on falling edge of update flag */
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while (CMOS_READ(RTC_REG_A) & RTC_UIP);
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while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
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count = read_c0_count() - start;
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/* restore interrupts */
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local_irq_restore(flags);
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#endif
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mips_hpt_frequency = count;
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if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
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(prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
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count *= 2;
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count += 5000; /* round */
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count -= count%10000;
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return count;
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}
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unsigned long __init mips_rtc_get_time(void)
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{
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return mc146818_get_cmos_time();
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}
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void __init mips_time_init(void)
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{
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unsigned int est_freq;
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/* Set Data mode - binary. */
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CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
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est_freq = estimate_cpu_frequency ();
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printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
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(est_freq%1000000)*100/1000000);
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cpu_khz = est_freq / 1000;
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mips_scroll_message();
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}
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irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
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{
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return perf_irq();
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}
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static struct irqaction perf_irqaction = {
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.handler = mips_perf_interrupt,
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.flags = IRQF_DISABLED | IRQF_PERCPU,
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.name = "performance",
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};
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void __init plat_perf_setup(struct irqaction *irq)
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{
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cp0_perfcount_irq = -1;
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#ifdef MSC01E_INT_BASE
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if (cpu_has_veic) {
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set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch);
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cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
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} else
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#endif
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if (cp0_perfcount_irq >= 0) {
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if (cpu_has_vint)
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set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_irq_smtc(cp0_perfcount_irq, irq,
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0x100 << cp0_perfcount_irq);
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#else
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setup_irq(cp0_perfcount_irq, irq);
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#endif /* CONFIG_MIPS_MT_SMTC */
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#ifdef CONFIG_SMP
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set_irq_handler(cp0_perfcount_irq, handle_percpu_irq);
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#endif
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}
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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#ifdef MSC01E_INT_BASE
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if (cpu_has_veic) {
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set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch);
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mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
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}
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else
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#endif
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{
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if (cpu_has_vint)
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set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
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mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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}
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/* we are using the cpu counter for timer interrupts */
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irq->handler = mips_timer_interrupt; /* we use our own handler */
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);
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#else
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setup_irq(mips_cpu_timer_irq, irq);
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#endif /* CONFIG_MIPS_MT_SMTC */
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#ifdef CONFIG_SMP
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set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
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#endif
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plat_perf_setup(&perf_irqaction);
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}
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