fa48f84a8c
Many aspects of the Blackfin memory map is exactly the same across all variants. Rather than copy and paste all of these duplicated values in each header, unify all of these into the common Blackfin memory map header file. In the process, push down BF561 SMP specific stuff to the BF561 specific header to keep the noise down. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
67 lines
2.3 KiB
C
67 lines
2.3 KiB
C
/*
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* File: include/asm-blackfin/mach-bf533/blackfin.h
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* Based on:
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* Author:
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*
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* Created:
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* Description:
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*
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* Rev:
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*
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* Modified:
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING.
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* If not, write to the Free Software Foundation,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef _MACH_BLACKFIN_H_
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#define _MACH_BLACKFIN_H_
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#define BF533_FAMILY
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#include "bf533.h"
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#include "defBF532.h"
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#include "anomaly.h"
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#if !defined(__ASSEMBLY__)
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#include "cdefBF532.h"
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#endif
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#define BFIN_UART_NR_PORTS 1
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#define CH_UART_RX CH_UART0_RX
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#define CH_UART_TX CH_UART0_TX
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#define IRQ_UART_ERROR IRQ_UART0_ERROR
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#define IRQ_UART_RX IRQ_UART0_RX
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#define IRQ_UART_TX IRQ_UART0_TX
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#define OFFSET_THR 0x00 /* Transmit Holding register */
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#define OFFSET_RBR 0x00 /* Receive Buffer register */
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#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
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#define OFFSET_IER 0x04 /* Interrupt Enable Register */
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#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
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#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
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#define OFFSET_LCR 0x0C /* Line Control Register */
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#define OFFSET_MCR 0x10 /* Modem Control Register */
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#define OFFSET_LSR 0x14 /* Line Status Register */
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#define OFFSET_MSR 0x18 /* Modem Status Register */
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#define OFFSET_SCR 0x1C /* SCR Scratch Register */
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#define OFFSET_GCTL 0x24 /* Global Control Register */
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#endif /* _MACH_BLACKFIN_H_ */
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