94dee171df
> #define hw_interrupt_type irq_chip > typedef struct irq_chip hw_irq_controller; > #define no_irq_type no_irq_chip > typedef struct irq_desc irq_desc_t; Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
440 lines
9.0 KiB
C
440 lines
9.0 KiB
C
/*
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* linux/arch/mps/tx4938/common/irq.c
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*
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* Common tx4938 irq handler
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/irq.h>
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#include <asm/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/tx4938/rbtx4938.h>
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/**********************************************************************************/
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/* Forwad definitions for all pic's */
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/**********************************************************************************/
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static unsigned int tx4938_irq_cp0_startup(unsigned int irq);
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static void tx4938_irq_cp0_shutdown(unsigned int irq);
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static void tx4938_irq_cp0_enable(unsigned int irq);
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static void tx4938_irq_cp0_disable(unsigned int irq);
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static void tx4938_irq_cp0_mask_and_ack(unsigned int irq);
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static void tx4938_irq_cp0_end(unsigned int irq);
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static unsigned int tx4938_irq_pic_startup(unsigned int irq);
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static void tx4938_irq_pic_shutdown(unsigned int irq);
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static void tx4938_irq_pic_enable(unsigned int irq);
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static void tx4938_irq_pic_disable(unsigned int irq);
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static void tx4938_irq_pic_mask_and_ack(unsigned int irq);
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static void tx4938_irq_pic_end(unsigned int irq);
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/**********************************************************************************/
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/* Kernel structs for all pic's */
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/**********************************************************************************/
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DEFINE_SPINLOCK(tx4938_cp0_lock);
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DEFINE_SPINLOCK(tx4938_pic_lock);
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#define TX4938_CP0_NAME "TX4938-CP0"
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static struct irq_chip tx4938_irq_cp0_type = {
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.typename = TX4938_CP0_NAME,
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.startup = tx4938_irq_cp0_startup,
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.shutdown = tx4938_irq_cp0_shutdown,
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.enable = tx4938_irq_cp0_enable,
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.disable = tx4938_irq_cp0_disable,
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.ack = tx4938_irq_cp0_mask_and_ack,
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.end = tx4938_irq_cp0_end,
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.set_affinity = NULL
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};
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#define TX4938_PIC_NAME "TX4938-PIC"
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static struct irq_chip tx4938_irq_pic_type = {
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.typename = TX4938_PIC_NAME,
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.startup = tx4938_irq_pic_startup,
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.shutdown = tx4938_irq_pic_shutdown,
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.enable = tx4938_irq_pic_enable,
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.disable = tx4938_irq_pic_disable,
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.ack = tx4938_irq_pic_mask_and_ack,
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.end = tx4938_irq_pic_end,
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.set_affinity = NULL
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};
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static struct irqaction tx4938_irq_pic_action = {
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.handler = no_action,
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.flags = 0,
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.mask = CPU_MASK_NONE,
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.name = TX4938_PIC_NAME
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};
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/**********************************************************************************/
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/* Functions for cp0 */
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/**********************************************************************************/
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#define tx4938_irq_cp0_mask(irq) ( 1 << ( irq-TX4938_IRQ_CP0_BEG+8 ) )
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static void __init
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tx4938_irq_cp0_init(void)
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{
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int i;
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for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &tx4938_irq_cp0_type;
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}
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return;
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}
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static unsigned int
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tx4938_irq_cp0_startup(unsigned int irq)
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{
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tx4938_irq_cp0_enable(irq);
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return (0);
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}
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static void
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tx4938_irq_cp0_shutdown(unsigned int irq)
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{
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tx4938_irq_cp0_disable(irq);
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}
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static void
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tx4938_irq_cp0_enable(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&tx4938_cp0_lock, flags);
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set_c0_status(tx4938_irq_cp0_mask(irq));
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spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
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}
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static void
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tx4938_irq_cp0_disable(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&tx4938_cp0_lock, flags);
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clear_c0_status(tx4938_irq_cp0_mask(irq));
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spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
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return;
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}
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static void
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tx4938_irq_cp0_mask_and_ack(unsigned int irq)
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{
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tx4938_irq_cp0_disable(irq);
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return;
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}
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static void
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tx4938_irq_cp0_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
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tx4938_irq_cp0_enable(irq);
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}
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return;
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}
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/**********************************************************************************/
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/* Functions for pic */
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/**********************************************************************************/
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u32
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tx4938_irq_pic_addr(int irq)
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{
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/* MVMCP -- need to formulize this */
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irq -= TX4938_IRQ_PIC_BEG;
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switch (irq) {
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case 17:
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case 16:
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case 1:
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case 0:{
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return (TX4938_MKA(TX4938_IRC_IRLVL0));
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}
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case 19:
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case 18:
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case 3:
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case 2:{
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return (TX4938_MKA(TX4938_IRC_IRLVL1));
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}
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case 21:
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case 20:
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case 5:
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case 4:{
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return (TX4938_MKA(TX4938_IRC_IRLVL2));
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}
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case 23:
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case 22:
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case 7:
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case 6:{
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return (TX4938_MKA(TX4938_IRC_IRLVL3));
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}
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case 25:
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case 24:
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case 9:
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case 8:{
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return (TX4938_MKA(TX4938_IRC_IRLVL4));
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}
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case 27:
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case 26:
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case 11:
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case 10:{
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return (TX4938_MKA(TX4938_IRC_IRLVL5));
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}
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case 29:
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case 28:
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case 13:
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case 12:{
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return (TX4938_MKA(TX4938_IRC_IRLVL6));
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}
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case 31:
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case 30:
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case 15:
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case 14:{
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return (TX4938_MKA(TX4938_IRC_IRLVL7));
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}
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}
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return (0);
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}
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u32
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tx4938_irq_pic_mask(int irq)
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{
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/* MVMCP -- need to formulize this */
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irq -= TX4938_IRQ_PIC_BEG;
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switch (irq) {
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case 31:
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case 29:
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case 27:
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case 25:
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case 23:
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case 21:
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case 19:
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case 17:{
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return (0x07000000);
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}
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case 30:
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case 28:
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case 26:
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case 24:
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case 22:
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case 20:
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case 18:
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case 16:{
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return (0x00070000);
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}
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case 15:
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case 13:
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case 11:
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case 9:
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case 7:
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case 5:
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case 3:
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case 1:{
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return (0x00000700);
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}
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case 14:
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case 12:
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case 10:
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case 8:
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case 6:
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case 4:
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case 2:
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case 0:{
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return (0x00000007);
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}
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}
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return (0x00000000);
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}
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static void
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tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
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{
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unsigned long val = 0;
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val = TX4938_RD(pic_reg);
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val &= (~clr_bits);
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val |= (set_bits);
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TX4938_WR(pic_reg, val);
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mmiowb();
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TX4938_RD(pic_reg);
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return;
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}
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static void __init
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tx4938_irq_pic_init(void)
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{
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unsigned long flags;
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int i;
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for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = 0;
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irq_desc[i].depth = 2;
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irq_desc[i].chip = &tx4938_irq_pic_type;
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}
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setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
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spin_lock_irqsave(&tx4938_pic_lock, flags);
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TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
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TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
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spin_unlock_irqrestore(&tx4938_pic_lock, flags);
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return;
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}
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static unsigned int
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tx4938_irq_pic_startup(unsigned int irq)
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{
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tx4938_irq_pic_enable(irq);
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return (0);
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}
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static void
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tx4938_irq_pic_shutdown(unsigned int irq)
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{
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tx4938_irq_pic_disable(irq);
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return;
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}
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static void
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tx4938_irq_pic_enable(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&tx4938_pic_lock, flags);
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tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
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tx4938_irq_pic_mask(irq));
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spin_unlock_irqrestore(&tx4938_pic_lock, flags);
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return;
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}
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static void
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tx4938_irq_pic_disable(unsigned int irq)
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{
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unsigned long flags;
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spin_lock_irqsave(&tx4938_pic_lock, flags);
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tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
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tx4938_irq_pic_mask(irq), 0);
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spin_unlock_irqrestore(&tx4938_pic_lock, flags);
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return;
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}
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static void
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tx4938_irq_pic_mask_and_ack(unsigned int irq)
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{
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tx4938_irq_pic_disable(irq);
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return;
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}
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static void
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tx4938_irq_pic_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
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tx4938_irq_pic_enable(irq);
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}
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return;
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}
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/**********************************************************************************/
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/* Main init functions */
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/**********************************************************************************/
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void __init
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tx4938_irq_init(void)
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{
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tx4938_irq_cp0_init();
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tx4938_irq_pic_init();
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return;
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}
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int
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tx4938_irq_nested(void)
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{
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int sw_irq = 0;
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u32 level2;
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level2 = TX4938_RD(0xff1ff6a0);
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if ((level2 & 0x10000) == 0) {
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level2 &= 0x1f;
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sw_irq = TX4938_IRQ_PIC_BEG + level2;
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if (sw_irq == 26) {
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{
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extern int toshiba_rbtx4938_irq_nested(int sw_irq);
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sw_irq = toshiba_rbtx4938_irq_nested(sw_irq);
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}
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}
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}
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wbflush();
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return (sw_irq);
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}
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asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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{
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unsigned int pending = read_c0_cause() & read_c0_status();
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if (pending & STATUSF_IP7)
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do_IRQ(TX4938_IRQ_CPU_TIMER, regs);
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else if (pending & STATUSF_IP2) {
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int irq = tx4938_irq_nested();
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if (irq)
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do_IRQ(irq, regs);
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else
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spurious_interrupt(regs);
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} else if (pending & STATUSF_IP1)
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do_IRQ(TX4938_IRQ_USER1, regs);
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else if (pending & STATUSF_IP0)
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do_IRQ(TX4938_IRQ_USER0, regs);
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}
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