3e7622f9d7
The array is never written, and on 64-bits it's not even being used past initial boot. Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
511 lines
13 KiB
C
511 lines
13 KiB
C
#include <linux/linkage.h>
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/sysdev.h>
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#include <linux/bitops.h>
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#include <asm/acpi.h>
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#include <asm/atomic.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/hw_irq.h>
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#include <asm/pgtable.h>
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#include <asm/delay.h>
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#include <asm/desc.h>
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#include <asm/apic.h>
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#include <asm/i8259.h>
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/*
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* Common place to define all x86 IRQ vectors
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*
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* This builds up the IRQ handler stubs using some ugly macros in irq.h
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*
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* These macros create the low-level assembly IRQ routines that save
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* register context and call do_IRQ(). do_IRQ() then does all the
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* operations that are needed to keep the AT (or SMP IOAPIC)
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* interrupt-controller happy.
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*/
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#define BI(x,y) \
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BUILD_IRQ(x##y)
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#define BUILD_16_IRQS(x) \
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BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
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BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
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BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
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BI(x,c) BI(x,d) BI(x,e) BI(x,f)
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/*
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* ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
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* (these are usually mapped to vectors 0x30-0x3f)
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*/
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/*
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* The IO-APIC gives us many more interrupt sources. Most of these
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* are unused but an SMP system is supposed to have enough memory ...
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* sometimes (mostly wrt. hw bugs) we get corrupted vectors all
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* across the spectrum, so we really want to be prepared to get all
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* of these. Plus, more powerful systems might have more than 64
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* IO-APIC registers.
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*
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* (these are usually mapped into the 0x30-0xff vector range)
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*/
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BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
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BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
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BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
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BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
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#undef BUILD_16_IRQS
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#undef BI
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#define IRQ(x,y) \
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IRQ##x##y##_interrupt
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#define IRQLIST_16(x) \
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IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
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IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
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IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
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IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
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/* for the irq vectors */
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static void (*__initdata interrupt[NR_VECTORS - FIRST_EXTERNAL_VECTOR])(void) = {
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IRQLIST_16(0x2), IRQLIST_16(0x3),
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IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
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IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
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IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
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};
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#undef IRQ
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#undef IRQLIST_16
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/*
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* This is the 'legacy' 8259A Programmable Interrupt Controller,
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* present in the majority of PC/AT boxes.
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* plus some generic x86 specific things if generic specifics makes
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* any sense at all.
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* this file should become arch/i386/kernel/irq.c when the old irq.c
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* moves to arch independent land
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*/
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static int i8259A_auto_eoi;
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DEFINE_SPINLOCK(i8259A_lock);
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static void mask_and_ack_8259A(unsigned int);
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static struct irq_chip i8259A_chip = {
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.name = "XT-PIC",
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.mask = disable_8259A_irq,
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.disable = disable_8259A_irq,
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.unmask = enable_8259A_irq,
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.mask_ack = mask_and_ack_8259A,
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};
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/*
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* 8259A PIC functions to handle ISA devices:
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*/
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/*
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* This contains the irq mask for both 8259A irq controllers,
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*/
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unsigned int cached_irq_mask = 0xffff;
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/*
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* Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
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* boards the timer interrupt is not really connected to any IO-APIC pin,
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* it's fed to the master 8259A's IR0 line only.
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*
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* Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
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* this 'mixed mode' IRQ handling costs nothing because it's only used
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* at IRQ setup time.
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*/
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unsigned long io_apic_irqs;
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void disable_8259A_irq(unsigned int irq)
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{
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unsigned int mask = 1 << irq;
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unsigned long flags;
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spin_lock_irqsave(&i8259A_lock, flags);
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cached_irq_mask |= mask;
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if (irq & 8)
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outb(cached_slave_mask, PIC_SLAVE_IMR);
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else
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outb(cached_master_mask, PIC_MASTER_IMR);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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void enable_8259A_irq(unsigned int irq)
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{
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unsigned int mask = ~(1 << irq);
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unsigned long flags;
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spin_lock_irqsave(&i8259A_lock, flags);
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cached_irq_mask &= mask;
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if (irq & 8)
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outb(cached_slave_mask, PIC_SLAVE_IMR);
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else
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outb(cached_master_mask, PIC_MASTER_IMR);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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int i8259A_irq_pending(unsigned int irq)
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{
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unsigned int mask = 1<<irq;
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&i8259A_lock, flags);
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if (irq < 8)
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ret = inb(PIC_MASTER_CMD) & mask;
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else
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ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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return ret;
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}
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void make_8259A_irq(unsigned int irq)
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{
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disable_irq_nosync(irq);
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io_apic_irqs &= ~(1<<irq);
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set_irq_chip_and_handler_name(irq, &i8259A_chip, handle_level_irq,
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"XT");
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enable_irq(irq);
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}
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/*
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* This function assumes to be called rarely. Switching between
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* 8259A registers is slow.
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* This has to be protected by the irq controller spinlock
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* before being called.
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*/
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static inline int i8259A_irq_real(unsigned int irq)
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{
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int value;
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int irqmask = 1<<irq;
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if (irq < 8) {
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outb(0x0B,PIC_MASTER_CMD); /* ISR register */
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value = inb(PIC_MASTER_CMD) & irqmask;
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outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */
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return value;
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}
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outb(0x0B,PIC_SLAVE_CMD); /* ISR register */
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value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
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outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */
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return value;
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}
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/*
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* Careful! The 8259A is a fragile beast, it pretty
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* much _has_ to be done exactly like this (mask it
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* first, _then_ send the EOI, and the order of EOI
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* to the two 8259s is important!
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*/
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static void mask_and_ack_8259A(unsigned int irq)
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{
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unsigned int irqmask = 1 << irq;
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unsigned long flags;
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spin_lock_irqsave(&i8259A_lock, flags);
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/*
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* Lightweight spurious IRQ detection. We do not want
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* to overdo spurious IRQ handling - it's usually a sign
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* of hardware problems, so we only do the checks we can
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* do without slowing down good hardware unnecessarily.
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*
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* Note that IRQ7 and IRQ15 (the two spurious IRQs
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* usually resulting from the 8259A-1|2 PICs) occur
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* even if the IRQ is masked in the 8259A. Thus we
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* can check spurious 8259A IRQs without doing the
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* quite slow i8259A_irq_real() call for every IRQ.
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* This does not cover 100% of spurious interrupts,
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* but should be enough to warn the user that there
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* is something bad going on ...
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*/
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if (cached_irq_mask & irqmask)
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goto spurious_8259A_irq;
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cached_irq_mask |= irqmask;
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handle_real_irq:
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if (irq & 8) {
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inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
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outb(cached_slave_mask, PIC_SLAVE_IMR);
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/* 'Specific EOI' to slave */
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outb(0x60+(irq&7),PIC_SLAVE_CMD);
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/* 'Specific EOI' to master-IRQ2 */
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outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD);
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} else {
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inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
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outb(cached_master_mask, PIC_MASTER_IMR);
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/* 'Specific EOI' to master */
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outb(0x60+irq,PIC_MASTER_CMD);
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}
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spin_unlock_irqrestore(&i8259A_lock, flags);
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return;
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spurious_8259A_irq:
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/*
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* this is the slow path - should happen rarely.
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*/
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if (i8259A_irq_real(irq))
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/*
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* oops, the IRQ _is_ in service according to the
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* 8259A - not spurious, go handle it.
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*/
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goto handle_real_irq;
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{
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static int spurious_irq_mask;
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/*
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* At this point we can be sure the IRQ is spurious,
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* lets ACK and report it. [once per IRQ]
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*/
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if (!(spurious_irq_mask & irqmask)) {
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printk(KERN_DEBUG
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"spurious 8259A interrupt: IRQ%d.\n", irq);
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spurious_irq_mask |= irqmask;
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}
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atomic_inc(&irq_err_count);
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/*
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* Theoretically we do not have to handle this IRQ,
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* but in Linux this does not cause problems and is
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* simpler for us.
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*/
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goto handle_real_irq;
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}
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}
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static char irq_trigger[2];
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/**
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* ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
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*/
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static void restore_ELCR(char *trigger)
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{
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outb(trigger[0], 0x4d0);
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outb(trigger[1], 0x4d1);
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}
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static void save_ELCR(char *trigger)
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{
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/* IRQ 0,1,2,8,13 are marked as reserved */
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trigger[0] = inb(0x4d0) & 0xF8;
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trigger[1] = inb(0x4d1) & 0xDE;
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}
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static int i8259A_resume(struct sys_device *dev)
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{
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init_8259A(i8259A_auto_eoi);
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restore_ELCR(irq_trigger);
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return 0;
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}
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static int i8259A_suspend(struct sys_device *dev, pm_message_t state)
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{
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save_ELCR(irq_trigger);
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return 0;
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}
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static int i8259A_shutdown(struct sys_device *dev)
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{
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/* Put the i8259A into a quiescent state that
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* the kernel initialization code can get it
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* out of.
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*/
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outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
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outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-1 */
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return 0;
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}
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static struct sysdev_class i8259_sysdev_class = {
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.name = "i8259",
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.suspend = i8259A_suspend,
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.resume = i8259A_resume,
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.shutdown = i8259A_shutdown,
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};
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static struct sys_device device_i8259A = {
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.id = 0,
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.cls = &i8259_sysdev_class,
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};
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static int __init i8259A_init_sysfs(void)
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{
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int error = sysdev_class_register(&i8259_sysdev_class);
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if (!error)
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error = sysdev_register(&device_i8259A);
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return error;
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}
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device_initcall(i8259A_init_sysfs);
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void init_8259A(int auto_eoi)
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{
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unsigned long flags;
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i8259A_auto_eoi = auto_eoi;
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spin_lock_irqsave(&i8259A_lock, flags);
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outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
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outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
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/*
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* outb_p - this has to work on a wide range of PC hardware.
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*/
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outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
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/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
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outb_p(IRQ0_VECTOR, PIC_MASTER_IMR);
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/* 8259A-1 (the master) has a slave on IR2 */
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outb_p(0x04, PIC_MASTER_IMR);
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if (auto_eoi) /* master does Auto EOI */
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outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
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else /* master expects normal EOI */
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outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
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outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
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/* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
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outb_p(IRQ8_VECTOR, PIC_SLAVE_IMR);
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/* 8259A-2 is a slave on master's IR2 */
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outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);
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/* (slave's support for AEOI in flat mode is to be investigated) */
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outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
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if (auto_eoi)
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/*
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* In AEOI mode we just have to mask the interrupt
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* when acking.
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*/
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i8259A_chip.mask_ack = disable_8259A_irq;
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else
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i8259A_chip.mask_ack = mask_and_ack_8259A;
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udelay(100); /* wait for 8259A to initialize */
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outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
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outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
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spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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/*
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* IRQ2 is cascade interrupt to second interrupt controller
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*/
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static struct irqaction irq2 = {
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.handler = no_action,
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.mask = CPU_MASK_NONE,
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.name = "cascade",
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};
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DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
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[0 ... IRQ0_VECTOR - 1] = -1,
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[IRQ0_VECTOR] = 0,
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[IRQ1_VECTOR] = 1,
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[IRQ2_VECTOR] = 2,
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[IRQ3_VECTOR] = 3,
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[IRQ4_VECTOR] = 4,
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[IRQ5_VECTOR] = 5,
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[IRQ6_VECTOR] = 6,
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[IRQ7_VECTOR] = 7,
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[IRQ8_VECTOR] = 8,
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[IRQ9_VECTOR] = 9,
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[IRQ10_VECTOR] = 10,
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[IRQ11_VECTOR] = 11,
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[IRQ12_VECTOR] = 12,
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[IRQ13_VECTOR] = 13,
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[IRQ14_VECTOR] = 14,
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[IRQ15_VECTOR] = 15,
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[IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
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};
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void __init init_ISA_irqs (void)
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{
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int i;
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init_bsp_APIC();
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init_8259A(0);
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for (i = 0; i < NR_IRQS; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = NULL;
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irq_desc[i].depth = 1;
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if (i < 16) {
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/*
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* 16 old-style INTA-cycle interrupts:
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*/
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set_irq_chip_and_handler_name(i, &i8259A_chip,
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handle_level_irq, "XT");
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} else {
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/*
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* 'high' PCI IRQs filled in on demand
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*/
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irq_desc[i].chip = &no_irq_chip;
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}
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}
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}
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void __init init_IRQ(void)
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{
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int i;
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init_ISA_irqs();
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/*
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* Cover the whole vector space, no vector can escape
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* us. (some of these will be overridden and become
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* 'special' SMP interrupts)
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*/
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for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
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int vector = FIRST_EXTERNAL_VECTOR + i;
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|
if (vector != IA32_SYSCALL_VECTOR)
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|
set_intr_gate(vector, interrupt[i]);
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
/*
|
|
* The reschedule interrupt is a CPU-to-CPU reschedule-helper
|
|
* IPI, driven by wakeup.
|
|
*/
|
|
set_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
|
|
|
|
/* IPIs for invalidation */
|
|
set_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
|
|
set_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
|
|
set_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
|
|
set_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
|
|
set_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
|
|
set_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
|
|
set_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
|
|
set_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
|
|
|
|
/* IPI for generic function call */
|
|
set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
|
|
|
|
/* Low priority IPI to cleanup after moving an irq */
|
|
set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
|
|
#endif
|
|
set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
|
|
set_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
|
|
|
|
/* self generated IPI for local APIC timer */
|
|
set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
|
|
|
|
/* IPI vectors for APIC spurious and error interrupts */
|
|
set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
|
|
set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
|
|
|
|
if (!acpi_ioapic)
|
|
setup_irq(2, &irq2);
|
|
}
|