366 lines
11 KiB
C
366 lines
11 KiB
C
/*
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* setup.c
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*
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* BRIEF MODULE DESCRIPTION
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* Momentum Computer Ocelot (CP7000) - board dependent boot routines
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*
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* Copyright (C) 1996, 1997, 2001, 06 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2000 RidgeRun, Inc.
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* Copyright (C) 2001 Red Hat, Inc.
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* Copyright (C) 2002 Momentum Computer
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*
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* Author: RidgeRun, Inc.
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* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/timex.h>
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#include <linux/vmalloc.h>
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#include <linux/pm.h>
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#include <asm/time.h>
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#include <asm/bootinfo.h>
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#include <asm/page.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/pci.h>
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#include <asm/processor.h>
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#include <asm/reboot.h>
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#include <asm/traps.h>
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#include <linux/bootmem.h>
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#include <linux/initrd.h>
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#include <asm/gt64120.h>
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#include "ocelot_pld.h"
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unsigned long gt64120_base = KSEG1ADDR(GT_DEF_BASE);
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/* These functions are used for rebooting or halting the machine*/
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extern void momenco_ocelot_restart(char *command);
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extern void momenco_ocelot_halt(void);
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extern void momenco_ocelot_power_off(void);
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extern void momenco_ocelot_irq_setup(void);
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static char reset_reason;
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#define ENTRYLO(x) ((pte_val(pfn_pte((x) >> PAGE_SHIFT, PAGE_KERNEL_UNCACHED)) >> 6)|1)
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static void __init setup_l3cache(unsigned long size);
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/* setup code for a handoff from a version 1 PMON 2000 PROM */
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void PMON_v1_setup()
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{
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/* A wired TLB entry for the GT64120A and the serial port. The
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GT64120A is going to be hit on every IRQ anyway - there's
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absolutely no point in letting it be a random TLB entry, as
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it'll just cause needless churning of the TLB. And we use
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the other half for the serial port, which is just a PITA
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otherwise :)
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Device Physical Virtual
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GT64120 Internal Regs 0x24000000 0xe0000000
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UARTs (CS2) 0x2d000000 0xe0001000
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*/
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add_wired_entry(ENTRYLO(0x24000000), ENTRYLO(0x2D000000), 0xe0000000, PM_4K);
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/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
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in the CS[012] region. We can't use ioremap() yet. The NVRAM
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is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
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Ocelot PLD (CS0) 0x2c000000 0xe0020000
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NVRAM 0x2c800000 0xe0030000
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*/
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add_temporary_entry(ENTRYLO(0x2C000000), ENTRYLO(0x2d000000), 0xe0020000, PM_64K);
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/* Relocate the CS3/BootCS region */
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GT_WRITE(GT_CS3BOOTLD_OFS, 0x2f000000 >> 21);
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/* Relocate CS[012] */
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GT_WRITE(GT_CS20LD_OFS, 0x2c000000 >> 21);
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/* Relocate the GT64120A itself... */
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GT_WRITE(GT_ISD_OFS, 0x24000000 >> 21);
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mb();
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gt64120_base = 0xe0000000;
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/* ...and the PCI0 view of it. */
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GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000020);
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GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000000);
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GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000024);
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GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x24000001);
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}
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/* setup code for a handoff from a version 2 PMON 2000 PROM */
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void PMON_v2_setup()
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{
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/* A wired TLB entry for the GT64120A and the serial port. The
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GT64120A is going to be hit on every IRQ anyway - there's
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absolutely no point in letting it be a random TLB entry, as
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it'll just cause needless churning of the TLB. And we use
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the other half for the serial port, which is just a PITA
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otherwise :)
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Device Physical Virtual
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GT64120 Internal Regs 0xf4000000 0xe0000000
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UARTs (CS2) 0xfd000000 0xe0001000
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*/
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add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xfD000000), 0xe0000000, PM_4K);
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/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
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in the CS[012] region. We can't use ioremap() yet. The NVRAM
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is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
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Ocelot PLD (CS0) 0xfc000000 0xe0020000
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NVRAM 0xfc800000 0xe0030000
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*/
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add_temporary_entry(ENTRYLO(0xfC000000), ENTRYLO(0xfd000000), 0xe0020000, PM_64K);
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gt64120_base = 0xe0000000;
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}
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void __init plat_mem_setup(void)
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{
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void (*l3func)(unsigned long)=KSEG1ADDR(&setup_l3cache);
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unsigned int tmpword;
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_machine_restart = momenco_ocelot_restart;
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_machine_halt = momenco_ocelot_halt;
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pm_power_off = momenco_ocelot_power_off;
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/*
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* initrd_start = (unsigned long)ocelot_initrd_start;
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* initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size;
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* initrd_below_start_ok = 1;
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*/
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/* do handoff reconfiguration */
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if (gt64120_base == KSEG1ADDR(GT_DEF_BASE))
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PMON_v1_setup();
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else
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PMON_v2_setup();
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/* Turn off the Bit-Error LED */
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OCELOT_PLD_WRITE(0x80, INTCLR);
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/* Relocate all the PCI1 stuff, not that we use it */
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GT_WRITE(GT_PCI1IOLD_OFS, 0x30000000 >> 21);
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GT_WRITE(GT_PCI1M0LD_OFS, 0x32000000 >> 21);
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GT_WRITE(GT_PCI1M1LD_OFS, 0x34000000 >> 21);
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/* Relocate PCI0 I/O and Mem0 */
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GT_WRITE(GT_PCI0IOLD_OFS, 0x20000000 >> 21);
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GT_WRITE(GT_PCI0M0LD_OFS, 0x22000000 >> 21);
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/* Relocate PCI0 Mem1 */
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GT_WRITE(GT_PCI0M1LD_OFS, 0x36000000 >> 21);
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/* For the initial programming, we assume 512MB configuration */
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/* Relocate the CPU's view of the RAM... */
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GT_WRITE(GT_SCS10LD_OFS, 0);
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GT_WRITE(GT_SCS10HD_OFS, 0x0fe00000 >> 21);
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GT_WRITE(GT_SCS32LD_OFS, 0x10000000 >> 21);
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GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
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GT_WRITE(GT_SCS1LD_OFS, 0xff);
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GT_WRITE(GT_SCS1HD_OFS, 0x00);
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GT_WRITE(GT_SCS0LD_OFS, 0);
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GT_WRITE(GT_SCS0HD_OFS, 0xff);
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GT_WRITE(GT_SCS3LD_OFS, 0xff);
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GT_WRITE(GT_SCS3HD_OFS, 0x00);
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GT_WRITE(GT_SCS2LD_OFS, 0);
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GT_WRITE(GT_SCS2HD_OFS, 0xff);
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/* ...and the PCI0 view of it. */
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GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000010);
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GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x00000000);
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GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
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GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x10000000);
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GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
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GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
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tmpword = OCELOT_PLD_READ(BOARDREV);
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if (tmpword < 26)
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printk("Momenco Ocelot: Board Assembly Rev. %c\n", 'A'+tmpword);
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else
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printk("Momenco Ocelot: Board Assembly Revision #0x%x\n", tmpword);
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tmpword = OCELOT_PLD_READ(PLD1_ID);
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printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
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tmpword = OCELOT_PLD_READ(PLD2_ID);
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printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
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tmpword = OCELOT_PLD_READ(RESET_STATUS);
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printk("Reset reason: 0x%x\n", tmpword);
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reset_reason = tmpword;
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OCELOT_PLD_WRITE(0xff, RESET_STATUS);
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tmpword = OCELOT_PLD_READ(BOARD_STATUS);
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printk("Board Status register: 0x%02x\n", tmpword);
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printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
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printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
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printk(" - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
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printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
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printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
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if (tmpword&12)
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l3func((1<<(((tmpword&12) >> 2)+20)));
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switch(tmpword &3) {
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case 3:
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/* 512MiB */
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/* Decoders are allready set -- just add the
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* appropriate region */
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add_memory_region( 0x40<<20, 0xC0<<20, BOOT_MEM_RAM);
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add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
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break;
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case 2:
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/* 256MiB -- two banks of 128MiB */
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GT_WRITE(GT_SCS10HD_OFS, 0x07e00000 >> 21);
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GT_WRITE(GT_SCS32LD_OFS, 0x08000000 >> 21);
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GT_WRITE(GT_SCS32HD_OFS, 0x0fe00000 >> 21);
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GT_WRITE(GT_SCS0HD_OFS, 0x7f);
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GT_WRITE(GT_SCS2LD_OFS, 0x80);
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GT_WRITE(GT_SCS2HD_OFS, 0xff);
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/* reconfigure the PCI0 interface view of memory */
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GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
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GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x08000000);
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GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x0ffff000);
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GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x0ffff000);
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add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
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add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
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break;
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case 1:
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/* 128MiB -- 64MiB per bank */
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GT_WRITE(GT_SCS10HD_OFS, 0x03e00000 >> 21);
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GT_WRITE(GT_SCS32LD_OFS, 0x04000000 >> 21);
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GT_WRITE(GT_SCS32HD_OFS, 0x07e00000 >> 21);
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GT_WRITE(GT_SCS0HD_OFS, 0x3f);
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GT_WRITE(GT_SCS2LD_OFS, 0x40);
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GT_WRITE(GT_SCS2HD_OFS, 0x7f);
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/* reconfigure the PCI0 interface view of memory */
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GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
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GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
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GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x03fff000);
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GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x03fff000);
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/* add the appropriate region */
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add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
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break;
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case 0:
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/* 64MiB */
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GT_WRITE(GT_SCS10HD_OFS, 0x01e00000 >> 21);
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GT_WRITE(GT_SCS32LD_OFS, 0x02000000 >> 21);
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GT_WRITE(GT_SCS32HD_OFS, 0x03e00000 >> 21);
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GT_WRITE(GT_SCS0HD_OFS, 0x1f);
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GT_WRITE(GT_SCS2LD_OFS, 0x20);
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GT_WRITE(GT_SCS2HD_OFS, 0x3f);
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/* reconfigure the PCI0 interface view of memory */
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GT_WRITE(GT_PCI0_CFGADDR_OFS, 0x80000014);
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GT_WRITE(GT_PCI0_CFGDATA_OFS, 0x04000000);
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GT_WRITE(GT_PCI0_BS_SCS10_OFS, 0x01fff000);
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GT_WRITE(GT_PCI0_BS_SCS32_OFS, 0x01fff000);
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break;
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}
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/* Fix up the DiskOnChip mapping */
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GT_WRITE(GT_DEV_B3_OFS, 0xfef73);
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}
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extern int rm7k_tcache_enabled;
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/*
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* This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
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*/
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#define Page_Invalidate_T 0x16
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static void __init setup_l3cache(unsigned long size)
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{
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int register i;
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unsigned long tmp;
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printk("Enabling L3 cache...");
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/* Enable the L3 cache in the GT64120A's CPU Configuration register */
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tmp = GT_READ(GT_CPU_OFS);
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GT_WRITE(GT_CPU_OFS, tmp | (1<<14));
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/* Enable the L3 cache in the CPU */
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set_c0_config(1<<12 /* CONF_TE */);
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/* Clear the cache */
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write_c0_taglo(0);
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write_c0_taghi(0);
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for (i=0; i < size; i+= 4096) {
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__asm__ __volatile__ (
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".set noreorder\n\t"
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".set mips3\n\t"
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"cache %1, (%0)\n\t"
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".set mips0\n\t"
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".set reorder"
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:
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: "r" (KSEG0ADDR(i)),
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"i" (Page_Invalidate_T));
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}
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/* Let the RM7000 MM code know that the tertiary cache is enabled */
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rm7k_tcache_enabled = 1;
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printk("Done\n");
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}
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/* This needs to be one of the first initcalls, because no I/O port access
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can work before this */
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static int io_base_ioremap(void)
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{
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void *io_remap_range = ioremap(GT_PCI_IO_BASE, GT_PCI_IO_SIZE);
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if (!io_remap_range) {
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panic("Could not ioremap I/O port range");
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}
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set_io_port_base(io_remap_range - GT_PCI_IO_BASE);
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return 0;
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}
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module_init(io_base_ioremap);
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