750ccf687f
Cacheflush(0, 0, 0) was crashing the system. This is because
flush_icache_range(start, end) tries to flushing whole address space
(0 - ~0UL) if both start and end are zero.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
154 lines
3.7 KiB
C
154 lines
3.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 - 2003 by Ralf Baechle
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/cacheflush.h>
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#include <asm/processor.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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/* Cache operations. */
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void (*flush_cache_all)(void);
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void (*__flush_cache_all)(void);
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void (*flush_cache_mm)(struct mm_struct *mm);
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void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
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unsigned long pfn);
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void (*flush_icache_range)(unsigned long __user start,
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unsigned long __user end);
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void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page);
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/* MIPS specific cache operations */
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void (*flush_cache_sigtramp)(unsigned long addr);
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void (*flush_data_cache_page)(unsigned long addr);
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void (*flush_icache_all)(void);
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EXPORT_SYMBOL(flush_data_cache_page);
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#ifdef CONFIG_DMA_NONCOHERENT
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/* DMA cache operations. */
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void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
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void (*_dma_cache_wback)(unsigned long start, unsigned long size);
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void (*_dma_cache_inv)(unsigned long start, unsigned long size);
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EXPORT_SYMBOL(_dma_cache_wback_inv);
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EXPORT_SYMBOL(_dma_cache_wback);
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EXPORT_SYMBOL(_dma_cache_inv);
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#endif /* CONFIG_DMA_NONCOHERENT */
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/*
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* We could optimize the case where the cache argument is not BCACHE but
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* that seems very atypical use ...
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*/
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asmlinkage int sys_cacheflush(unsigned long __user addr,
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unsigned long bytes, unsigned int cache)
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{
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if (bytes == 0)
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return 0;
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if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes))
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return -EFAULT;
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flush_icache_range(addr, addr + bytes);
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return 0;
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}
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void __flush_dcache_page(struct page *page)
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{
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struct address_space *mapping = page_mapping(page);
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unsigned long addr;
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if (mapping && !mapping_mapped(mapping)) {
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SetPageDcacheDirty(page);
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return;
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}
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/*
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* We could delay the flush for the !page_mapping case too. But that
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* case is for exec env/arg pages and those are %99 certainly going to
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* get faulted into the tlb (and thus flushed) anyways.
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*/
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addr = (unsigned long) page_address(page);
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flush_data_cache_page(addr);
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}
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EXPORT_SYMBOL(__flush_dcache_page);
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void __update_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t pte)
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{
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struct page *page;
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unsigned long pfn, addr;
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pfn = pte_pfn(pte);
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if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page_mapping(page)) &&
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Page_dcache_dirty(page)) {
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if (pages_do_alias((unsigned long)page_address(page),
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address & PAGE_MASK)) {
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addr = (unsigned long) page_address(page);
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flush_data_cache_page(addr);
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}
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ClearPageDcacheDirty(page);
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}
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}
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#define __weak __attribute__((weak))
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static char cache_panic[] __initdata = "Yeee, unsupported cache architecture.";
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void __init cpu_cache_init(void)
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{
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if (cpu_has_3k_cache) {
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extern void __weak r3k_cache_init(void);
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r3k_cache_init();
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return;
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}
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if (cpu_has_6k_cache) {
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extern void __weak r6k_cache_init(void);
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r6k_cache_init();
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return;
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}
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if (cpu_has_4k_cache) {
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extern void __weak r4k_cache_init(void);
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r4k_cache_init();
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return;
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}
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if (cpu_has_8k_cache) {
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extern void __weak r8k_cache_init(void);
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r8k_cache_init();
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return;
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}
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if (cpu_has_tx39_cache) {
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extern void __weak tx39_cache_init(void);
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tx39_cache_init();
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return;
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}
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if (cpu_has_sb1_cache) {
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extern void __weak sb1_cache_init(void);
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sb1_cache_init();
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return;
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}
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panic(cache_panic);
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}
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