42c059e04d
_raw_spin_lock_flags() is entered with interrupts disabled. If it cannot
obtain a spinlock, it checks the flags that were passed and re-enables
interrupts before spinning if that's how the flags are set. When the
spinlock might be available, it disables interrupts (even if they are
already disabled) before trying to get the lock. Change that so interrupts
are only disabled if they have been enabled. This costs nine bytes of
duplicated spinloop code.
Fastpath before patch:
jle <keep looping> not-taken conditional jump
cli disable interrupts
jmp <try for lock> unconditional jump
Fastpath after patch, if interrupts were not enabled:
jg <try for lock> taken conditional branch
Signed-off-by: Chuck Ebbert <76306.1226@compuserve.com>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
201 lines
4.3 KiB
C
201 lines
4.3 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/atomic.h>
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#include <asm/rwlock.h>
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#include <asm/page.h>
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#include <linux/config.h>
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#include <linux/compiler.h>
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*
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* (the type definitions are in asm/spinlock_types.h)
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*/
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#define __raw_spin_is_locked(x) \
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(*(volatile signed char *)(&(x)->slock) <= 0)
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#define __raw_spin_lock_string \
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"\n1:\t" \
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"lock ; decb %0\n\t" \
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"jns 3f\n" \
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"2:\t" \
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"rep;nop\n\t" \
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"cmpb $0,%0\n\t" \
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"jle 2b\n\t" \
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"jmp 1b\n" \
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"3:\n\t"
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#define __raw_spin_lock_string_flags \
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"\n1:\t" \
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"lock ; decb %0\n\t" \
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"jns 5f\n" \
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"2:\t" \
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"testl $0x200, %1\n\t" \
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"jz 4f\n\t" \
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"sti\n" \
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"3:\t" \
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"rep;nop\n\t" \
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"cmpb $0, %0\n\t" \
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"jle 3b\n\t" \
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"cli\n\t" \
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"jmp 1b\n" \
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"4:\t" \
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"rep;nop\n\t" \
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"cmpb $0, %0\n\t" \
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"jg 1b\n\t" \
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"jmp 4b\n" \
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"5:\n\t"
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#define __raw_spin_lock_string_up \
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"\n\tdecb %0"
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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alternative_smp(
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__raw_spin_lock_string,
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__raw_spin_lock_string_up,
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"=m" (lock->slock) : : "memory");
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}
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static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
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{
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alternative_smp(
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__raw_spin_lock_string_flags,
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__raw_spin_lock_string_up,
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"=m" (lock->slock) : "r" (flags) : "memory");
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}
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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char oldval;
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__asm__ __volatile__(
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"xchgb %b0,%1"
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:"=q" (oldval), "=m" (lock->slock)
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:"0" (0) : "memory");
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return oldval > 0;
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}
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/*
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* __raw_spin_unlock based on writing $1 to the low byte.
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* This method works. Despite all the confusion.
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* (except on PPro SMP or if we are using OOSTORE, so we use xchgb there)
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* (PPro errata 66, 92)
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*/
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#if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
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#define __raw_spin_unlock_string \
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"movb $1,%0" \
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:"=m" (lock->slock) : : "memory"
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__(
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__raw_spin_unlock_string
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);
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}
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#else
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#define __raw_spin_unlock_string \
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"xchgb %b0, %1" \
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:"=q" (oldval), "=m" (lock->slock) \
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:"0" (oldval) : "memory"
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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char oldval = 1;
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__asm__ __volatile__(
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__raw_spin_unlock_string
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);
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}
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#endif
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*
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* On x86, we implement read-write locks as a 32-bit counter
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* with the high bit (sign) being the "contended" bit.
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*
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* The inline assembly is non-obvious. Think about it.
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*
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* Changed to use the same technique as rw semaphores. See
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* semaphore.h for details. -ben
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*
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* the helpers are in arch/i386/kernel/semaphore.c
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*/
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/**
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* read_can_lock - would read_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define __raw_read_can_lock(x) ((int)(x)->lock > 0)
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/**
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* write_can_lock - would write_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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__build_read_lock(rw, "__read_lock_failed");
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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__build_write_lock(rw, "__write_lock_failed");
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}
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static inline int __raw_read_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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atomic_dec(count);
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if (atomic_read(count) >= 0)
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return 1;
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atomic_inc(count);
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return 0;
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}
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static inline int __raw_write_trylock(raw_rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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if (atomic_sub_and_test(RW_LOCK_BIAS, count))
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return 1;
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atomic_add(RW_LOCK_BIAS, count);
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return 0;
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}
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX "incl %0" :"=m" (rw->lock) : : "memory");
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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asm volatile(LOCK_PREFIX "addl $" RW_LOCK_BIAS_STR ", %0"
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: "=m" (rw->lock) : : "memory");
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}
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#endif /* __ASM_SPINLOCK_H */
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