f15cbe6f1a
This follows the sparc changes a439fe51a1
.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
98 lines
1.8 KiB
C
98 lines
1.8 KiB
C
#ifndef __ASM_SH_CLOCK_H
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#define __ASM_SH_CLOCK_H
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#include <linux/kref.h>
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#include <linux/list.h>
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#include <linux/seq_file.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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struct clk;
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struct clk_ops {
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void (*init)(struct clk *clk);
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void (*enable)(struct clk *clk);
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void (*disable)(struct clk *clk);
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void (*recalc)(struct clk *clk);
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int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
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long (*round_rate)(struct clk *clk, unsigned long rate);
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};
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struct clk {
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struct list_head node;
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const char *name;
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int id;
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struct module *owner;
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struct clk *parent;
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struct clk_ops *ops;
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struct kref kref;
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unsigned long rate;
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unsigned long flags;
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unsigned long arch_flags;
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};
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#define CLK_ALWAYS_ENABLED (1 << 0)
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#define CLK_RATE_PROPAGATES (1 << 1)
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/* Should be defined by processor-specific code */
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void arch_init_clk_ops(struct clk_ops **, int type);
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/* arch/sh/kernel/cpu/clock.c */
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int clk_init(void);
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void clk_recalc_rate(struct clk *);
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int clk_register(struct clk *);
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void clk_unregister(struct clk *);
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static inline int clk_always_enable(const char *id)
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{
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struct clk *clk;
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int ret;
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clk = clk_get(NULL, id);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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ret = clk_enable(clk);
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if (ret)
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clk_put(clk);
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return ret;
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}
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/* the exported API, in addition to clk_set_rate */
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/**
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* clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
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* @clk: clock source
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* @rate: desired clock rate in Hz
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* @algo_id: algorithm id to be passed down to ops->set_rate
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*
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* Returns success (0) or negative errno.
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*/
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int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
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enum clk_sh_algo_id {
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NO_CHANGE = 0,
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IUS_N1_N1,
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IUS_322,
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IUS_522,
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IUS_N11,
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SB_N1,
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SB3_N1,
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SB3_32,
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SB3_43,
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SB3_54,
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BP_N1,
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IP_N1,
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};
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#endif /* __ASM_SH_CLOCK_H */
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