97dcb82de6
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
130 lines
3.7 KiB
C
130 lines
3.7 KiB
C
/*
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* Copyright (C) by Basler Vision Technologies AG
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* Author: Thomas Koeller <thomas.koeller@baslereb.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <asm/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/rm9k-ocd.h>
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#include <excite.h>
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extern asmlinkage void excite_handle_int(void);
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/*
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* Initialize the interrupt handler
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*/
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init();
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rm7k_cpu_irq_init();
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rm9k_cpu_irq_init();
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#ifdef CONFIG_KGDB
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excite_kgdb_init();
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#endif
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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const u32
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interrupts = read_c0_cause() >> 8,
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mask = ((read_c0_status() >> 8) & 0x000000ff) |
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(read_c0_intcontrol() & 0x0000ff00),
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pending = interrupts & mask;
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u32 msgintflags, msgintmask, msgint;
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/* process timer interrupt */
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if (pending & (1 << TIMER_IRQ)) {
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do_IRQ(TIMER_IRQ);
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return;
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}
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/* Process PCI interrupts */
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#if USB_IRQ < 10
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msgintflags = ocd_readl(INTP0Status0 + (USB_MSGINT / 0x20 * 0x10));
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msgintmask = ocd_readl(INTP0Mask0 + (USB_MSGINT / 0x20 * 0x10));
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msgint = msgintflags & msgintmask & (0x1 << (USB_MSGINT % 0x20));
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if ((pending & (1 << USB_IRQ)) && msgint) {
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#else
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if (pending & (1 << USB_IRQ)) {
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#endif
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do_IRQ(USB_IRQ);
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return;
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}
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/* Process TITAN interrupts */
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msgintflags = ocd_readl(INTP0Status0 + (TITAN_MSGINT / 0x20 * 0x10));
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msgintmask = ocd_readl(INTP0Mask0 + (TITAN_MSGINT / 0x20 * 0x10));
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msgint = msgintflags & msgintmask & (0x1 << (TITAN_MSGINT % 0x20));
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if ((pending & (1 << TITAN_IRQ)) && msgint) {
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ocd_writel(msgint, INTP0Clear0 + (TITAN_MSGINT / 0x20 * 0x10));
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#if defined(CONFIG_KGDB)
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excite_kgdb_inthdl();
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#endif
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do_IRQ(TITAN_IRQ);
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return;
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}
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/* Process FPGA line #0 interrupts */
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msgintflags = ocd_readl(INTP0Status0 + (FPGA0_MSGINT / 0x20 * 0x10));
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msgintmask = ocd_readl(INTP0Mask0 + (FPGA0_MSGINT / 0x20 * 0x10));
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msgint = msgintflags & msgintmask & (0x1 << (FPGA0_MSGINT % 0x20));
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if ((pending & (1 << FPGA0_IRQ)) && msgint) {
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do_IRQ(FPGA0_IRQ);
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return;
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}
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/* Process FPGA line #1 interrupts */
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msgintflags = ocd_readl(INTP0Status0 + (FPGA1_MSGINT / 0x20 * 0x10));
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msgintmask = ocd_readl(INTP0Mask0 + (FPGA1_MSGINT / 0x20 * 0x10));
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msgint = msgintflags & msgintmask & (0x1 << (FPGA1_MSGINT % 0x20));
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if ((pending & (1 << FPGA1_IRQ)) && msgint) {
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do_IRQ(FPGA1_IRQ);
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return;
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}
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/* Process PHY interrupts */
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msgintflags = ocd_readl(INTP0Status0 + (PHY_MSGINT / 0x20 * 0x10));
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msgintmask = ocd_readl(INTP0Mask0 + (PHY_MSGINT / 0x20 * 0x10));
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msgint = msgintflags & msgintmask & (0x1 << (PHY_MSGINT % 0x20));
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if ((pending & (1 << PHY_IRQ)) && msgint) {
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do_IRQ(PHY_IRQ);
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return;
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}
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/* Process spurious interrupts */
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spurious_interrupt();
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}
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