f1d3d38af7
Add support for other versions of the 10G Chelsio boards. This is basically a port of the vendor driver with the TOE features removed. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
159 lines
6.7 KiB
C
159 lines
6.7 KiB
C
/*****************************************************************************
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* *
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* File: elmer0.h *
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* $Revision: 1.6 $ *
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* $Date: 2005/06/21 22:49:43 $ *
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* Description: *
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* part of the Chelsio 10Gb Ethernet Driver. *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License, version 2, as *
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* published by the Free Software Foundation. *
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* *
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* You should have received a copy of the GNU General Public License along *
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* with this program; if not, write to the Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* *
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
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* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
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* *
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* http://www.chelsio.com *
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* *
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* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
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* All rights reserved. *
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* *
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* Maintainers: maintainers@chelsio.com *
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* *
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* Authors: Dimitrios Michailidis <dm@chelsio.com> *
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* Tina Yang <tainay@chelsio.com> *
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* Felix Marti <felix@chelsio.com> *
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* Scott Bardone <sbardone@chelsio.com> *
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* Kurt Ottaway <kottaway@chelsio.com> *
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* Frank DiMambro <frank@chelsio.com> *
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* *
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* History: *
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* *
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****************************************************************************/
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#ifndef _CXGB_ELMER0_H_
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#define _CXGB_ELMER0_H_
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/* ELMER0 flavors */
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enum {
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ELMER0_XC2S300E_6FT256_C,
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ELMER0_XC2S100E_6TQ144_C
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};
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/* ELMER0 registers */
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#define A_ELMER0_VERSION 0x100000
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#define A_ELMER0_PHY_CFG 0x100004
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#define A_ELMER0_INT_ENABLE 0x100008
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#define A_ELMER0_INT_CAUSE 0x10000c
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#define A_ELMER0_GPI_CFG 0x100010
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#define A_ELMER0_GPI_STAT 0x100014
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#define A_ELMER0_GPO 0x100018
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#define A_ELMER0_PORT0_MI1_CFG 0x400000
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#define S_MI1_MDI_ENABLE 0
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#define V_MI1_MDI_ENABLE(x) ((x) << S_MI1_MDI_ENABLE)
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#define F_MI1_MDI_ENABLE V_MI1_MDI_ENABLE(1U)
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#define S_MI1_MDI_INVERT 1
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#define V_MI1_MDI_INVERT(x) ((x) << S_MI1_MDI_INVERT)
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#define F_MI1_MDI_INVERT V_MI1_MDI_INVERT(1U)
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#define S_MI1_PREAMBLE_ENABLE 2
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#define V_MI1_PREAMBLE_ENABLE(x) ((x) << S_MI1_PREAMBLE_ENABLE)
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#define F_MI1_PREAMBLE_ENABLE V_MI1_PREAMBLE_ENABLE(1U)
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#define S_MI1_SOF 3
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#define M_MI1_SOF 0x3
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#define V_MI1_SOF(x) ((x) << S_MI1_SOF)
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#define G_MI1_SOF(x) (((x) >> S_MI1_SOF) & M_MI1_SOF)
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#define S_MI1_CLK_DIV 5
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#define M_MI1_CLK_DIV 0xff
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#define V_MI1_CLK_DIV(x) ((x) << S_MI1_CLK_DIV)
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#define G_MI1_CLK_DIV(x) (((x) >> S_MI1_CLK_DIV) & M_MI1_CLK_DIV)
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#define A_ELMER0_PORT0_MI1_ADDR 0x400004
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#define S_MI1_REG_ADDR 0
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#define M_MI1_REG_ADDR 0x1f
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#define V_MI1_REG_ADDR(x) ((x) << S_MI1_REG_ADDR)
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#define G_MI1_REG_ADDR(x) (((x) >> S_MI1_REG_ADDR) & M_MI1_REG_ADDR)
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#define S_MI1_PHY_ADDR 5
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#define M_MI1_PHY_ADDR 0x1f
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#define V_MI1_PHY_ADDR(x) ((x) << S_MI1_PHY_ADDR)
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#define G_MI1_PHY_ADDR(x) (((x) >> S_MI1_PHY_ADDR) & M_MI1_PHY_ADDR)
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#define A_ELMER0_PORT0_MI1_DATA 0x400008
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#define S_MI1_DATA 0
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#define M_MI1_DATA 0xffff
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#define V_MI1_DATA(x) ((x) << S_MI1_DATA)
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#define G_MI1_DATA(x) (((x) >> S_MI1_DATA) & M_MI1_DATA)
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#define A_ELMER0_PORT0_MI1_OP 0x40000c
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#define S_MI1_OP 0
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#define M_MI1_OP 0x3
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#define V_MI1_OP(x) ((x) << S_MI1_OP)
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#define G_MI1_OP(x) (((x) >> S_MI1_OP) & M_MI1_OP)
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#define S_MI1_ADDR_AUTOINC 2
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#define V_MI1_ADDR_AUTOINC(x) ((x) << S_MI1_ADDR_AUTOINC)
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#define F_MI1_ADDR_AUTOINC V_MI1_ADDR_AUTOINC(1U)
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#define S_MI1_OP_BUSY 31
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#define V_MI1_OP_BUSY(x) ((x) << S_MI1_OP_BUSY)
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#define F_MI1_OP_BUSY V_MI1_OP_BUSY(1U)
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#define A_ELMER0_PORT1_MI1_CFG 0x500000
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#define A_ELMER0_PORT1_MI1_ADDR 0x500004
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#define A_ELMER0_PORT1_MI1_DATA 0x500008
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#define A_ELMER0_PORT1_MI1_OP 0x50000c
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#define A_ELMER0_PORT2_MI1_CFG 0x600000
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#define A_ELMER0_PORT2_MI1_ADDR 0x600004
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#define A_ELMER0_PORT2_MI1_DATA 0x600008
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#define A_ELMER0_PORT2_MI1_OP 0x60000c
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#define A_ELMER0_PORT3_MI1_CFG 0x700000
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#define A_ELMER0_PORT3_MI1_ADDR 0x700004
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#define A_ELMER0_PORT3_MI1_DATA 0x700008
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#define A_ELMER0_PORT3_MI1_OP 0x70000c
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/* Simple bit definition for GPI and GP0 registers. */
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#define ELMER0_GP_BIT0 0x0001
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#define ELMER0_GP_BIT1 0x0002
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#define ELMER0_GP_BIT2 0x0004
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#define ELMER0_GP_BIT3 0x0008
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#define ELMER0_GP_BIT4 0x0010
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#define ELMER0_GP_BIT5 0x0020
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#define ELMER0_GP_BIT6 0x0040
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#define ELMER0_GP_BIT7 0x0080
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#define ELMER0_GP_BIT8 0x0100
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#define ELMER0_GP_BIT9 0x0200
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#define ELMER0_GP_BIT10 0x0400
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#define ELMER0_GP_BIT11 0x0800
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#define ELMER0_GP_BIT12 0x1000
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#define ELMER0_GP_BIT13 0x2000
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#define ELMER0_GP_BIT14 0x4000
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#define ELMER0_GP_BIT15 0x8000
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#define ELMER0_GP_BIT16 0x10000
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#define ELMER0_GP_BIT17 0x20000
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#define ELMER0_GP_BIT18 0x40000
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#define ELMER0_GP_BIT19 0x80000
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#define MI1_OP_DIRECT_WRITE 1
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#define MI1_OP_DIRECT_READ 2
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#define MI1_OP_INDIRECT_ADDRESS 0
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#define MI1_OP_INDIRECT_WRITE 1
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#define MI1_OP_INDIRECT_READ_INC 2
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#define MI1_OP_INDIRECT_READ 3
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#endif /* _CXGB_ELMER0_H_ */
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