android_kernel_xiaomi_sm8350/arch/sh/kernel/cpu
Stuart Menefy cbaa118ecf sh: Preparation for uncached jumps through PMB.
Presently most of the 29-bit physical parts do P1/P2 segmentation
with a 1:1 cached/uncached mapping, jumping between the two to
control the caching behaviour. This provides the basic infrastructure
to maintain this behaviour on 32-bit physical parts that don't map
P1/P2 at all, using a shiny new linker section and corresponding
fixmap entry.

Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:18:59 +09:00
..
irq sh: comment tidying for sh64->sh migration. 2008-01-28 13:18:58 +09:00
sh2 sh: SH-2A FPU support. 2008-01-28 13:18:57 +09:00
sh2a sh: SH-2A FPU support. 2008-01-28 13:18:57 +09:00
sh3 sh: Preparation for uncached jumps through PMB. 2008-01-28 13:18:59 +09:00
sh4 sh: SH-2A FPU support. 2008-01-28 13:18:57 +09:00
sh4a
sh5 sh: comment tidying for sh64->sh migration. 2008-01-28 13:18:58 +09:00
adc.c
clock.c
init.c sh: Preparation for uncached jumps through PMB. 2008-01-28 13:18:59 +09:00
Makefile sh: Move over the SH-5 entry.S. 2008-01-28 13:18:46 +09:00
ubc.S