a09e64fbc0
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
527 lines
13 KiB
C
527 lines
13 KiB
C
/*
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* OMAP3-specific clock framework functions
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2008 Nokia Corporation
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*
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* Written by Paul Walmsley
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* Testing and integration fixes by Jouni Högander
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/limits.h>
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#include <mach/clock.h>
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#include <mach/sram.h>
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#include <asm/div64.h>
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#include <asm/bitops.h>
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#include "memory.h"
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#include "clock.h"
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#include "clock34xx.h"
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#include "prm.h"
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#include "prm-regbits-34xx.h"
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
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#define DPLL_AUTOIDLE_DISABLE 0x0
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#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
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#define MAX_DPLL_WAIT_TRIES 1000000
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/**
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* omap3_dpll_recalc - recalculate DPLL rate
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* @clk: DPLL struct clk
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*
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* Recalculate and propagate the DPLL rate.
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*/
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static void omap3_dpll_recalc(struct clk *clk)
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{
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clk->rate = omap2_get_dpll_rate(clk);
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propagate_rate(clk);
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}
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/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
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static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
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{
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const struct dpll_data *dd;
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dd = clk->dpll_data;
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cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),
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dd->control_reg);
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}
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/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
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static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
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{
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const struct dpll_data *dd;
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int i = 0;
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int ret = -EINVAL;
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u32 idlest_mask;
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dd = clk->dpll_data;
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state <<= dd->idlest_bit;
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idlest_mask = 1 << dd->idlest_bit;
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while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) &&
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i < MAX_DPLL_WAIT_TRIES) {
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i++;
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udelay(1);
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}
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if (i == MAX_DPLL_WAIT_TRIES) {
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printk(KERN_ERR "clock: %s failed transition to '%s'\n",
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clk->name, (state) ? "locked" : "bypassed");
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} else {
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pr_debug("clock: %s transition to '%s' in %d loops\n",
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clk->name, (state) ? "locked" : "bypassed", i);
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ret = 0;
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}
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return ret;
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}
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/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
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/*
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* _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
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* @clk: pointer to a DPLL struct clk
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*
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* Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
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* readiness before returning. Will save and restore the DPLL's
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* autoidle state across the enable, per the CDP code. If the DPLL
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* locked successfully, return 0; if the DPLL did not lock in the time
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* allotted, or DPLL3 was passed in, return -EINVAL.
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*/
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static int _omap3_noncore_dpll_lock(struct clk *clk)
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{
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u8 ai;
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int r;
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if (clk == &dpll3_ck)
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return -EINVAL;
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pr_debug("clock: locking DPLL %s\n", clk->name);
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ai = omap3_dpll_autoidle_read(clk);
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_omap3_dpll_write_clken(clk, DPLL_LOCKED);
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if (ai) {
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/*
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* If no downstream clocks are enabled, CM_IDLEST bit
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* may never become active, so don't wait for DPLL to lock.
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*/
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r = 0;
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omap3_dpll_allow_idle(clk);
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} else {
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r = _omap3_wait_dpll_status(clk, 1);
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omap3_dpll_deny_idle(clk);
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};
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return r;
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}
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/*
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* omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
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* @clk: pointer to a DPLL struct clk
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*
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* Instructs a non-CORE DPLL to enter low-power bypass mode. In
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* bypass mode, the DPLL's rate is set equal to its parent clock's
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* rate. Waits for the DPLL to report readiness before returning.
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* Will save and restore the DPLL's autoidle state across the enable,
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* per the CDP code. If the DPLL entered bypass mode successfully,
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* return 0; if the DPLL did not enter bypass in the time allotted, or
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* DPLL3 was passed in, or the DPLL does not support low-power bypass,
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* return -EINVAL.
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*/
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static int _omap3_noncore_dpll_bypass(struct clk *clk)
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{
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int r;
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u8 ai;
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if (clk == &dpll3_ck)
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return -EINVAL;
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if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
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return -EINVAL;
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pr_debug("clock: configuring DPLL %s for low-power bypass\n",
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clk->name);
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ai = omap3_dpll_autoidle_read(clk);
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_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
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r = _omap3_wait_dpll_status(clk, 0);
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if (ai)
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omap3_dpll_allow_idle(clk);
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else
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omap3_dpll_deny_idle(clk);
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return r;
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}
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/*
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* _omap3_noncore_dpll_stop - instruct a DPLL to stop
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* @clk: pointer to a DPLL struct clk
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*
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* Instructs a non-CORE DPLL to enter low-power stop. Will save and
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* restore the DPLL's autoidle state across the stop, per the CDP
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* code. If DPLL3 was passed in, or the DPLL does not support
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* low-power stop, return -EINVAL; otherwise, return 0.
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*/
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static int _omap3_noncore_dpll_stop(struct clk *clk)
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{
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u8 ai;
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if (clk == &dpll3_ck)
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return -EINVAL;
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if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
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return -EINVAL;
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pr_debug("clock: stopping DPLL %s\n", clk->name);
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ai = omap3_dpll_autoidle_read(clk);
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_omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
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if (ai)
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omap3_dpll_allow_idle(clk);
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else
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omap3_dpll_deny_idle(clk);
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return 0;
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}
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/**
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* omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
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* @clk: pointer to a DPLL struct clk
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*
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* Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
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* The choice of modes depends on the DPLL's programmed rate: if it is
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* the same as the DPLL's parent clock, it will enter bypass;
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* otherwise, it will enter lock. This code will wait for the DPLL to
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* indicate readiness before returning, unless the DPLL takes too long
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* to enter the target state. Intended to be used as the struct clk's
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* enable function. If DPLL3 was passed in, or the DPLL does not
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* support low-power stop, or if the DPLL took too long to enter
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* bypass or lock, return -EINVAL; otherwise, return 0.
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*/
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static int omap3_noncore_dpll_enable(struct clk *clk)
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{
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int r;
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if (clk == &dpll3_ck)
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return -EINVAL;
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if (clk->parent->rate == clk_get_rate(clk))
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r = _omap3_noncore_dpll_bypass(clk);
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else
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r = _omap3_noncore_dpll_lock(clk);
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return r;
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}
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/**
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* omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
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* @clk: pointer to a DPLL struct clk
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*
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* Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
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* The choice of modes depends on the DPLL's programmed rate: if it is
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* the same as the DPLL's parent clock, it will enter bypass;
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* otherwise, it will enter lock. This code will wait for the DPLL to
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* indicate readiness before returning, unless the DPLL takes too long
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* to enter the target state. Intended to be used as the struct clk's
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* enable function. If DPLL3 was passed in, or the DPLL does not
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* support low-power stop, or if the DPLL took too long to enter
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* bypass or lock, return -EINVAL; otherwise, return 0.
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*/
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static void omap3_noncore_dpll_disable(struct clk *clk)
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{
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if (clk == &dpll3_ck)
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return;
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_omap3_noncore_dpll_stop(clk);
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}
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/**
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* omap3_dpll_autoidle_read - read a DPLL's autoidle bits
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* @clk: struct clk * of the DPLL to read
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*
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* Return the DPLL's autoidle bits, shifted down to bit 0. Returns
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* -EINVAL if passed a null pointer or if the struct clk does not
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* appear to refer to a DPLL.
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*/
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static u32 omap3_dpll_autoidle_read(struct clk *clk)
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{
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const struct dpll_data *dd;
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u32 v;
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if (!clk || !clk->dpll_data)
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return -EINVAL;
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dd = clk->dpll_data;
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v = cm_read_reg(dd->autoidle_reg);
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v &= dd->autoidle_mask;
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v >>= __ffs(dd->autoidle_mask);
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return v;
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}
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/**
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* omap3_dpll_allow_idle - enable DPLL autoidle bits
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* @clk: struct clk * of the DPLL to operate on
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*
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* Enable DPLL automatic idle control. This automatic idle mode
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* switching takes effect only when the DPLL is locked, at least on
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* OMAP3430. The DPLL will enter low-power stop when its downstream
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* clocks are gated. No return value.
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*/
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static void omap3_dpll_allow_idle(struct clk *clk)
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{
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const struct dpll_data *dd;
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if (!clk || !clk->dpll_data)
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return;
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dd = clk->dpll_data;
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/*
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* REVISIT: CORE DPLL can optionally enter low-power bypass
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* by writing 0x5 instead of 0x1. Add some mechanism to
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* optionally enter this mode.
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*/
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cm_rmw_reg_bits(dd->autoidle_mask,
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DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),
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dd->autoidle_reg);
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}
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/**
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* omap3_dpll_deny_idle - prevent DPLL from automatically idling
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* @clk: struct clk * of the DPLL to operate on
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*
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* Disable DPLL automatic idle control. No return value.
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*/
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static void omap3_dpll_deny_idle(struct clk *clk)
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{
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const struct dpll_data *dd;
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if (!clk || !clk->dpll_data)
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return;
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dd = clk->dpll_data;
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cm_rmw_reg_bits(dd->autoidle_mask,
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DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),
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dd->autoidle_reg);
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}
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/* Clock control for DPLL outputs */
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/**
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* omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
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* @clk: DPLL output struct clk
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*
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* Using parent clock DPLL data, look up DPLL state. If locked, set our
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* rate to the dpll_clk * 2; otherwise, just use dpll_clk.
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*/
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static void omap3_clkoutx2_recalc(struct clk *clk)
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{
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const struct dpll_data *dd;
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u32 v;
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struct clk *pclk;
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/* Walk up the parents of clk, looking for a DPLL */
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pclk = clk->parent;
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while (pclk && !pclk->dpll_data)
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pclk = pclk->parent;
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/* clk does not have a DPLL as a parent? */
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WARN_ON(!pclk);
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dd = pclk->dpll_data;
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WARN_ON(!dd->control_reg || !dd->enable_mask);
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v = __raw_readl(dd->control_reg) & dd->enable_mask;
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v >>= __ffs(dd->enable_mask);
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if (v != DPLL_LOCKED)
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clk->rate = clk->parent->rate;
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else
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clk->rate = clk->parent->rate * 2;
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if (clk->flags & RATE_PROPAGATES)
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propagate_rate(clk);
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}
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/* Common clock code */
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/*
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* As it is structured now, this will prevent an OMAP2/3 multiboot
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* kernel from compiling. This will need further attention.
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*/
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#if defined(CONFIG_ARCH_OMAP3)
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static struct clk_functions omap2_clk_functions = {
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.clk_enable = omap2_clk_enable,
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.clk_disable = omap2_clk_disable,
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.clk_round_rate = omap2_clk_round_rate,
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.clk_set_rate = omap2_clk_set_rate,
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.clk_set_parent = omap2_clk_set_parent,
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.clk_disable_unused = omap2_clk_disable_unused,
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};
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/*
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* Set clocks for bypass mode for reboot to work.
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*/
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void omap2_clk_prepare_for_reboot(void)
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{
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/* REVISIT: Not ready for 343x */
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#if 0
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u32 rate;
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if (vclk == NULL || sclk == NULL)
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return;
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rate = clk_get_rate(sclk);
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clk_set_rate(vclk, rate);
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#endif
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}
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/* REVISIT: Move this init stuff out into clock.c */
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/*
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* Switch the MPU rate if specified on cmdline.
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* We cannot do this early until cmdline is parsed.
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*/
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static int __init omap2_clk_arch_init(void)
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{
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if (!mpurate)
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return -EINVAL;
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/* REVISIT: not yet ready for 343x */
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#if 0
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if (omap2_select_table_rate(&virt_prcm_set, mpurate))
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printk(KERN_ERR "Could not find matching MPU rate\n");
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#endif
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recalculate_root_clocks();
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printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL3/MPU): "
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"%ld.%01ld/%ld/%ld MHz\n",
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(osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
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(core_ck.rate / 1000000), (dpll1_fck.rate / 1000000)) ;
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return 0;
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}
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arch_initcall(omap2_clk_arch_init);
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int __init omap2_clk_init(void)
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{
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/* struct prcm_config *prcm; */
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struct clk **clkp;
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/* u32 clkrate; */
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u32 cpu_clkflg;
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/* REVISIT: Ultimately this will be used for multiboot */
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#if 0
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if (cpu_is_omap242x()) {
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cpu_mask = RATE_IN_242X;
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cpu_clkflg = CLOCK_IN_OMAP242X;
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clkp = onchip_24xx_clks;
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} else if (cpu_is_omap2430()) {
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cpu_mask = RATE_IN_243X;
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cpu_clkflg = CLOCK_IN_OMAP243X;
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clkp = onchip_24xx_clks;
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}
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#endif
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if (cpu_is_omap34xx()) {
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cpu_mask = RATE_IN_343X;
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cpu_clkflg = CLOCK_IN_OMAP343X;
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clkp = onchip_34xx_clks;
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/*
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* Update this if there are further clock changes between ES2
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* and production parts
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*/
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if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
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/* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
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cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
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} else {
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cpu_mask |= RATE_IN_3430ES2;
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cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
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}
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}
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clk_init(&omap2_clk_functions);
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for (clkp = onchip_34xx_clks;
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clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
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clkp++) {
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if ((*clkp)->flags & cpu_clkflg)
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clk_register(*clkp);
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}
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/* REVISIT: Not yet ready for OMAP3 */
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#if 0
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/* Check the MPU rate set by bootloader */
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clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
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for (prcm = rate_table; prcm->mpu_speed; prcm++) {
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if (!(prcm->flags & cpu_mask))
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continue;
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if (prcm->xtal_speed != sys_ck.rate)
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continue;
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if (prcm->dpll_speed <= clkrate)
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break;
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}
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curr_prcm_set = prcm;
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#endif
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recalculate_root_clocks();
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printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
|
|
"%ld.%01ld/%ld/%ld MHz\n",
|
|
(osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
|
|
(core_ck.rate / 1000000), (arm_fck.rate / 1000000));
|
|
|
|
/*
|
|
* Only enable those clocks we will need, let the drivers
|
|
* enable other clocks as necessary
|
|
*/
|
|
clk_enable_init_clocks();
|
|
|
|
/* Avoid sleeping during omap2_clk_prepare_for_reboot() */
|
|
/* REVISIT: not yet ready for 343x */
|
|
#if 0
|
|
vclk = clk_get(NULL, "virt_prcm_set");
|
|
sclk = clk_get(NULL, "sys_ck");
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#endif
|