12fb0eb4c9
Adds IFM PDM360NG device tree and platform code. Currently following is supported: - Spansion S29GL512P 256 MB NOR flash - ST Micro NAND 1 GiB flash - DIU, please use "fbcon=map:5 video=fslfb:800x480-32@60" at the kernel command line to enable PrimeView PM070WL3 Display support. - FEC - I2C - RTC, EEPROM - MSCAN - PSC UART, please pass "console=tty0 console=ttyPSC5,115200" on the kernel command line. - SPI, ADS7845 Touchscreen - USB0/1 Host - USB0 OTG Host/Device - VIU, Overlay/Capture support Signed-off-by: Markus Fischer <markus.fischer.ec@ifm.com> Signed-off-by: Wolfgang Grandegger <wg@denx.de> Signed-off-by: Michael Weiss <michael.weiss@ifm.com> Signed-off-by: Detlev Zundel <dzu@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
411 lines
8.5 KiB
Plaintext
411 lines
8.5 KiB
Plaintext
/*
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* Device Tree Source for IFM PDM360NG.
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*
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* Copyright 2009 - 2010 DENX Software Engineering.
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* Anatolij Gustschin <agust@denx.de>
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*
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* Based on MPC5121E ADS dts.
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* Copyright 2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "pdm360ng";
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compatible = "ifm,pdm360ng";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&ipic>;
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aliases {
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ethernet0 = ð0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,5121@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <0x20>; // 32 bytes
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i-cache-line-size = <0x20>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
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bus-frequency = <198000000>; // 198 MHz csb bus
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clock-frequency = <396000000>; // 396 MHz ppc core
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>; // 512MB at 0
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};
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nfc@40000000 {
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compatible = "fsl,mpc5121-nfc";
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reg = <0x40000000 0x100000>;
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interrupts = <0x6 0x8>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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bank-width = <0x1>;
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chips = <0x1>;
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partition@0 {
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label = "nand0";
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reg = <0x0 0x40000000>;
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};
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};
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sram@50000000 {
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compatible = "fsl,mpc5121-sram";
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reg = <0x50000000 0x20000>; // 128K at 0x50000000
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};
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localbus@80000020 {
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compatible = "fsl,mpc5121-localbus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0x80000020 0x40>;
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ranges = <0x0 0x0 0xf0000000 0x10000000 /* Flash */
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0x2 0x0 0x50040000 0x00020000>; /* CS2: MRAM */
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flash@0,0 {
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compatible = "amd,s29gl01gp", "cfi-flash";
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reg = <0 0x00000000 0x08000000
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0 0x08000000 0x08000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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bank-width = <4>;
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device-width = <2>;
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partition@0 {
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label = "u-boot";
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reg = <0x00000000 0x00080000>;
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read-only;
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};
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partition@80000 {
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label = "environment";
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reg = <0x00080000 0x00080000>;
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read-only;
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};
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partition@100000 {
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label = "splash-image";
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reg = <0x00100000 0x00080000>;
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read-only;
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};
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partition@180000 {
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label = "device-tree";
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reg = <0x00180000 0x00040000>;
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};
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partition@1c0000 {
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label = "kernel";
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reg = <0x001c0000 0x00500000>;
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};
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partition@6c0000 {
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label = "filesystem";
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reg = <0x006c0000 0x07940000>;
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};
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};
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mram0@2,0 {
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compatible = "mtd-ram";
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reg = <2 0x00000 0x10000>;
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bank-width = <2>;
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};
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mram1@2,10000 {
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compatible = "mtd-ram";
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reg = <2 0x010000 0x10000>;
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bank-width = <2>;
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};
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};
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soc@80000000 {
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compatible = "fsl,mpc5121-immr";
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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ranges = <0x0 0x80000000 0x400000>;
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reg = <0x80000000 0x400000>;
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bus-frequency = <66000000>; // 66 MHz ips bus
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// IPIC
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// interrupts cell = <intr #, sense>
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// sense values match linux IORESOURCE_IRQ_* defines:
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// sense == 8: Level, low assertion
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// sense == 2: Edge, high-to-low change
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//
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ipic: interrupt-controller@c00 {
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compatible = "fsl,mpc5121-ipic", "fsl,ipic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0xc00 0x100>;
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};
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rtc@a00 { // Real time clock
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compatible = "fsl,mpc5121-rtc";
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reg = <0xa00 0x100>;
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interrupts = <79 0x8 80 0x8>;
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};
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reset@e00 { // Reset module
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compatible = "fsl,mpc5121-reset";
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reg = <0xe00 0x100>;
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};
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clock@f00 { // Clock control
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compatible = "fsl,mpc5121-clock";
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reg = <0xf00 0x100>;
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};
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pmc@1000{ //Power Management Controller
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compatible = "fsl,mpc5121-pmc";
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reg = <0x1000 0x100>;
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interrupts = <83 0x2>;
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};
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gpio@1100 {
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compatible = "fsl,mpc5121-gpio";
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reg = <0x1100 0x100>;
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interrupts = <78 0x8>;
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};
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can@1300 {
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compatible = "fsl,mpc5121-mscan";
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interrupts = <12 0x8>;
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reg = <0x1300 0x80>;
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};
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can@1380 {
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compatible = "fsl,mpc5121-mscan";
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interrupts = <13 0x8>;
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reg = <0x1380 0x80>;
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};
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i2c@1700 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c";
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reg = <0x1700 0x20>;
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interrupts = <0x9 0x8>;
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fsl,preserve-clocking;
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eeprom@50 {
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compatible = "at,24c01";
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reg = <0x50>;
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};
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rtc@68 {
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compatible = "stm,m41t00";
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reg = <0x68>;
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};
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};
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i2c@1740 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c";
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reg = <0x1740 0x20>;
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interrupts = <0xb 0x8>;
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fsl,preserve-clocking;
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};
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i2ccontrol@1760 {
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compatible = "fsl,mpc5121-i2c-ctrl";
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reg = <0x1760 0x8>;
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};
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axe@2000 {
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compatible = "fsl,mpc5121-axe";
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reg = <0x2000 0x100>;
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interrupts = <42 0x8>;
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};
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display@2100 {
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compatible = "fsl,mpc5121-diu";
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reg = <0x2100 0x100>;
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interrupts = <64 0x8>;
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};
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can@2300 {
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compatible = "fsl,mpc5121-mscan";
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interrupts = <90 0x8>;
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reg = <0x2300 0x80>;
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};
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can@2380 {
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compatible = "fsl,mpc5121-mscan";
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interrupts = <91 0x8>;
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reg = <0x2380 0x80>;
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};
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viu@2400 {
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compatible = "fsl,mpc5121-viu";
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reg = <0x2400 0x400>;
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interrupts = <67 0x8>;
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};
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mdio@2800 {
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compatible = "fsl,mpc5121-fec-mdio";
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reg = <0x2800 0x200>;
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#address-cells = <1>;
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#size-cells = <0>;
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phy: ethernet-phy@0 {
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compatible = "smsc,lan8700";
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reg = <0x1f>;
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};
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};
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eth0: ethernet@2800 {
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compatible = "fsl,mpc5121-fec";
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reg = <0x2800 0x200>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <4 0x8>;
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phy-handle = < &phy >;
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};
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// USB1 using external ULPI PHY
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usb@3000 {
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compatible = "fsl,mpc5121-usb2-dr";
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reg = <0x3000 0x600>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <43 0x8>;
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dr_mode = "host";
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phy_type = "ulpi";
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};
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// USB0 using internal UTMI PHY
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usb@4000 {
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compatible = "fsl,mpc5121-usb2-dr";
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reg = <0x4000 0x600>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <44 0x8>;
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dr_mode = "otg";
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phy_type = "utmi_wide";
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fsl,invert-pwr-fault;
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};
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// IO control
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ioctl@a000 {
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compatible = "fsl,mpc5121-ioctl";
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reg = <0xA000 0x1000>;
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};
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// 512x PSCs are not 52xx PSCs compatible
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serial@11000 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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cell-index = <0>;
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reg = <0x11000 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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serial@11100 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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cell-index = <1>;
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reg = <0x11100 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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serial@11200 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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cell-index = <2>;
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reg = <0x11200 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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serial@11300 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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cell-index = <3>;
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reg = <0x11300 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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serial@11400 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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cell-index = <4>;
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reg = <0x11400 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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serial@11600 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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cell-index = <6>;
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reg = <0x11600 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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serial@11800 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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cell-index = <8>;
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reg = <0x11800 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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serial@11B00 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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cell-index = <11>;
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reg = <0x11B00 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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};
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pscfifo@11f00 {
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compatible = "fsl,mpc5121-psc-fifo";
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reg = <0x11f00 0x100>;
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interrupts = <40 0x8>;
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};
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spi@11900 {
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compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
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cell-index = <9>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x11900 0x100>;
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interrupts = <40 0x8>;
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fsl,rx-fifo-size = <16>;
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fsl,tx-fifo-size = <16>;
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// 7845 touch screen controller
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ts@0 {
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compatible = "ti,ads7846";
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reg = <0x0>;
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spi-max-frequency = <3000000>;
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// pen irq is GPIO25
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interrupts = <78 0x8>;
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};
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};
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dma@14000 {
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compatible = "fsl,mpc5121-dma";
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reg = <0x14000 0x1800>;
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interrupts = <65 0x8>;
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};
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};
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};
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