1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
160 lines
4.1 KiB
C
160 lines
4.1 KiB
C
/*
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* arch/mips/ddb5074/irq.c -- NEC DDB Vrc-5074 interrupt routines
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*
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* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
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* Sony Software Development Center Europe (SDCE), Brussels
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <asm/i8259.h>
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#include <asm/io.h>
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#include <asm/irq_cpu.h>
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#include <asm/ptrace.h>
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#include <asm/nile4.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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#include <asm/ddb5xxx/ddb5074.h>
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extern asmlinkage void ddbIRQ(void);
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static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
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#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
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#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
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#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
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#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
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#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
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#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
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#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
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#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
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#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
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#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
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#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
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#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
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static void m1543_irq_setup(void)
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{
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/*
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* The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
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* the possible IO sources in the M1543 are in use by us. We will
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* use the following mapping:
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*
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* IRQ1 - keyboard (default set by M1543)
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* IRQ3 - reserved for UART B (default set by M1543) (note that
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* the schematics for the DDB Vrc-5074 board seem to
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* indicate that IRQ3 is connected to the DS1386
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* watchdog timer interrupt output so we might have
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* a conflict)
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* IRQ4 - reserved for UART A (default set by M1543)
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* IRQ5 - parallel (default set by M1543)
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* IRQ8 - DS1386 time of day (RTC) interrupt
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* IRQ12 - mouse
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*/
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/*
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* Assing mouse interrupt to IRQ12
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*/
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/* Enter configuration mode */
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outb(0x51, M1543_PNP_CONFIG);
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outb(0x23, M1543_PNP_CONFIG);
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/* Select logical device 7 (Keyboard) */
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outb(0x07, M1543_PNP_INDEX);
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outb(0x07, M1543_PNP_DATA);
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/* Select IRQ12 */
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outb(0x72, M1543_PNP_INDEX);
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outb(0x0c, M1543_PNP_DATA);
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outb(0x30, M1543_PNP_INDEX);
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printk("device 7, 0x30: %02x\n",inb(M1543_PNP_DATA));
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outb(0x70, M1543_PNP_INDEX);
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printk("device 7, 0x70: %02x\n",inb(M1543_PNP_DATA));
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/* Leave configration mode */
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outb(0xbb, M1543_PNP_CONFIG);
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}
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void ddb_local0_irqdispatch(struct pt_regs *regs)
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{
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u32 mask;
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int nile4_irq;
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mask = nile4_get_irq_stat(0);
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/* Handle the timer interrupt first */
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#if 0
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if (mask & (1 << NILE4_INT_GPT)) {
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do_IRQ(nile4_to_irq(NILE4_INT_GPT), regs);
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mask &= ~(1 << NILE4_INT_GPT);
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}
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#endif
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for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1)
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if (mask & 1) {
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if (nile4_irq == NILE4_INT_INTE) {
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int i8259_irq;
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nile4_clear_irq(NILE4_INT_INTE);
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i8259_irq = nile4_i8259_iack();
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do_IRQ(i8259_irq, regs);
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} else
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do_IRQ(nile4_to_irq(nile4_irq), regs);
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}
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}
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void ddb_local1_irqdispatch(void)
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{
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printk("ddb_local1_irqdispatch called\n");
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}
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void ddb_buserror_irq(void)
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{
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printk("ddb_buserror_irq called\n");
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}
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void ddb_8254timer_irq(void)
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{
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printk("ddb_8254timer_irq called\n");
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}
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void __init arch_init_irq(void)
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{
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/* setup cascade interrupts */
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setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade);
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setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade);
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set_except_vector(0, ddbIRQ);
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nile4_irq_setup(NILE4_IRQ_BASE);
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m1543_irq_setup();
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init_i8259_irqs();
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printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE);
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mips_cpu_irq_init(CPU_IRQ_BASE);
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printk("enabling 8259 cascade\n");
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ddb5074_led_hex(0);
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/* Enable the interrupt cascade */
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nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE);
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}
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