909 lines
23 KiB
C
909 lines
23 KiB
C
/*
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* linux/arch/arm/plat-omap/mcbsp.c
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*
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* Copyright (C) 2004 Nokia Corporation
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* Author: Samuel Ortiz <samuel.ortiz@nokia.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Multichannel mode not supported.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/wait.h>
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <mach/dma.h>
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#include <mach/mcbsp.h>
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static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
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#define omap_mcbsp_check_valid_id(id) (mcbsp[id].pdata && \
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mcbsp[id].pdata->ops && \
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mcbsp[id].pdata->ops->check && \
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(mcbsp[id].pdata->ops->check(id) == 0))
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static void omap_mcbsp_dump_reg(u8 id)
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{
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dev_dbg(mcbsp[id].dev, "**** McBSP%d regs ****\n", mcbsp[id].id);
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dev_dbg(mcbsp[id].dev, "DRR2: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
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dev_dbg(mcbsp[id].dev, "DRR1: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
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dev_dbg(mcbsp[id].dev, "DXR2: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
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dev_dbg(mcbsp[id].dev, "DXR1: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
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dev_dbg(mcbsp[id].dev, "SPCR2: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
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dev_dbg(mcbsp[id].dev, "SPCR1: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
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dev_dbg(mcbsp[id].dev, "RCR2: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
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dev_dbg(mcbsp[id].dev, "RCR1: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
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dev_dbg(mcbsp[id].dev, "XCR2: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
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dev_dbg(mcbsp[id].dev, "XCR1: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
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dev_dbg(mcbsp[id].dev, "SRGR2: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
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dev_dbg(mcbsp[id].dev, "SRGR1: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
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dev_dbg(mcbsp[id].dev, "PCR0: 0x%04x\n",
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OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
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dev_dbg(mcbsp[id].dev, "***********************\n");
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}
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static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
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{
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struct omap_mcbsp *mcbsp_tx = dev_id;
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dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n",
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OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
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complete(&mcbsp_tx->tx_irq_completion);
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return IRQ_HANDLED;
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}
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static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
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{
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struct omap_mcbsp *mcbsp_rx = dev_id;
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dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n",
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OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
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complete(&mcbsp_rx->rx_irq_completion);
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return IRQ_HANDLED;
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}
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static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
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{
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struct omap_mcbsp *mcbsp_dma_tx = data;
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dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
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OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
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/* We can free the channels */
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omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
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mcbsp_dma_tx->dma_tx_lch = -1;
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complete(&mcbsp_dma_tx->tx_dma_completion);
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}
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static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
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{
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struct omap_mcbsp *mcbsp_dma_rx = data;
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dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
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OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
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/* We can free the channels */
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omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
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mcbsp_dma_rx->dma_rx_lch = -1;
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complete(&mcbsp_dma_rx->rx_dma_completion);
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}
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/*
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* omap_mcbsp_config simply write a config to the
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* appropriate McBSP.
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* You either call this function or set the McBSP registers
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* by yourself before calling omap_mcbsp_start().
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*/
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void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
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{
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void __iomem *io_base;
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if (!omap_mcbsp_check_valid_id(id)) {
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printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
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return;
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}
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io_base = mcbsp[id].io_base;
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dev_dbg(mcbsp[id].dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
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mcbsp[id].id, mcbsp[id].phys_base);
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/* We write the given config */
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OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
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OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
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OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
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OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
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OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
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OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
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OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
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OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
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OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
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OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
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OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
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}
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EXPORT_SYMBOL(omap_mcbsp_config);
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/*
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* We can choose between IRQ based or polled IO.
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* This needs to be called before omap_mcbsp_request().
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*/
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int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
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{
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if (!omap_mcbsp_check_valid_id(id)) {
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printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
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return -ENODEV;
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}
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spin_lock(&mcbsp[id].lock);
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if (!mcbsp[id].free) {
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dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
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mcbsp[id].id);
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spin_unlock(&mcbsp[id].lock);
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return -EINVAL;
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}
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mcbsp[id].io_type = io_type;
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spin_unlock(&mcbsp[id].lock);
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return 0;
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}
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EXPORT_SYMBOL(omap_mcbsp_set_io_type);
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int omap_mcbsp_request(unsigned int id)
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{
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int err;
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if (!omap_mcbsp_check_valid_id(id)) {
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printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
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return -ENODEV;
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}
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if (mcbsp[id].pdata->ops->request)
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mcbsp[id].pdata->ops->request(id);
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clk_enable(mcbsp[id].clk);
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spin_lock(&mcbsp[id].lock);
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if (!mcbsp[id].free) {
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dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
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mcbsp[id].id);
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spin_unlock(&mcbsp[id].lock);
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return -1;
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}
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mcbsp[id].free = 0;
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spin_unlock(&mcbsp[id].lock);
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if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
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/* We need to get IRQs here */
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err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler,
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0, "McBSP", (void *) (&mcbsp[id]));
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if (err != 0) {
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dev_err(mcbsp[id].dev, "Unable to request TX IRQ %d "
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"for McBSP%d\n", mcbsp[id].tx_irq,
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mcbsp[id].id);
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return err;
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}
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init_completion(&(mcbsp[id].tx_irq_completion));
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err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler,
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0, "McBSP", (void *) (&mcbsp[id]));
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if (err != 0) {
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dev_err(mcbsp[id].dev, "Unable to request RX IRQ %d "
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"for McBSP%d\n", mcbsp[id].rx_irq,
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mcbsp[id].id);
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free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
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return err;
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}
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init_completion(&(mcbsp[id].rx_irq_completion));
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}
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return 0;
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}
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EXPORT_SYMBOL(omap_mcbsp_request);
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void omap_mcbsp_free(unsigned int id)
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{
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if (!omap_mcbsp_check_valid_id(id)) {
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printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
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return;
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}
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if (mcbsp[id].pdata->ops->free)
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mcbsp[id].pdata->ops->free(id);
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clk_disable(mcbsp[id].clk);
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spin_lock(&mcbsp[id].lock);
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if (mcbsp[id].free) {
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dev_err(mcbsp[id].dev, "McBSP%d was not reserved\n",
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mcbsp[id].id);
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spin_unlock(&mcbsp[id].lock);
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return;
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}
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mcbsp[id].free = 1;
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spin_unlock(&mcbsp[id].lock);
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if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
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/* Free IRQs */
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free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
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free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
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}
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}
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EXPORT_SYMBOL(omap_mcbsp_free);
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/*
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* Here we start the McBSP, by enabling the sample
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* generator, both transmitter and receivers,
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* and the frame sync.
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*/
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void omap_mcbsp_start(unsigned int id)
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{
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void __iomem *io_base;
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u16 w;
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if (!omap_mcbsp_check_valid_id(id)) {
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printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
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return;
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}
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io_base = mcbsp[id].io_base;
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mcbsp[id].rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
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mcbsp[id].tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
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/* Start the sample generator */
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w = OMAP_MCBSP_READ(io_base, SPCR2);
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OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
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/* Enable transmitter and receiver */
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w = OMAP_MCBSP_READ(io_base, SPCR2);
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OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
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w = OMAP_MCBSP_READ(io_base, SPCR1);
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OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
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udelay(100);
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/* Start frame sync */
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w = OMAP_MCBSP_READ(io_base, SPCR2);
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OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
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/* Dump McBSP Regs */
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omap_mcbsp_dump_reg(id);
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}
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EXPORT_SYMBOL(omap_mcbsp_start);
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void omap_mcbsp_stop(unsigned int id)
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{
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void __iomem *io_base;
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u16 w;
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if (!omap_mcbsp_check_valid_id(id)) {
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printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
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return;
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}
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io_base = mcbsp[id].io_base;
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/* Reset transmitter */
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w = OMAP_MCBSP_READ(io_base, SPCR2);
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OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
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/* Reset receiver */
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w = OMAP_MCBSP_READ(io_base, SPCR1);
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OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
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/* Reset the sample rate generator */
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w = OMAP_MCBSP_READ(io_base, SPCR2);
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OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
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}
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EXPORT_SYMBOL(omap_mcbsp_stop);
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/* polled mcbsp i/o operations */
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int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
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{
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void __iomem *base;
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if (!omap_mcbsp_check_valid_id(id)) {
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printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
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return -ENODEV;
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}
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base = mcbsp[id].io_base;
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writew(buf, base + OMAP_MCBSP_REG_DXR1);
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/* if frame sync error - clear the error */
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if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
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/* clear error */
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writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
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base + OMAP_MCBSP_REG_SPCR2);
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/* resend */
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return -1;
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} else {
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/* wait for transmit confirmation */
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int attemps = 0;
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while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
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if (attemps++ > 1000) {
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writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
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(~XRST),
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base + OMAP_MCBSP_REG_SPCR2);
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udelay(10);
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writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
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(XRST),
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base + OMAP_MCBSP_REG_SPCR2);
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udelay(10);
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dev_err(mcbsp[id].dev, "Could not write to"
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" McBSP%d Register\n", mcbsp[id].id);
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return -2;
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}
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}
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}
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return 0;
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}
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EXPORT_SYMBOL(omap_mcbsp_pollwrite);
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int omap_mcbsp_pollread(unsigned int id, u16 *buf)
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{
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void __iomem *base;
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if (!omap_mcbsp_check_valid_id(id)) {
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printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
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return -ENODEV;
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}
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base = mcbsp[id].io_base;
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/* if frame sync error - clear the error */
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if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
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/* clear error */
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writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
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base + OMAP_MCBSP_REG_SPCR1);
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/* resend */
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return -1;
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} else {
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/* wait for recieve confirmation */
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int attemps = 0;
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while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
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if (attemps++ > 1000) {
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writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
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(~RRST),
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base + OMAP_MCBSP_REG_SPCR1);
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udelay(10);
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writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
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(RRST),
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base + OMAP_MCBSP_REG_SPCR1);
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udelay(10);
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dev_err(mcbsp[id].dev, "Could not read from"
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" McBSP%d Register\n", mcbsp[id].id);
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return -2;
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}
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}
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}
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*buf = readw(base + OMAP_MCBSP_REG_DRR1);
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return 0;
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}
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EXPORT_SYMBOL(omap_mcbsp_pollread);
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/*
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* IRQ based word transmission.
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*/
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void omap_mcbsp_xmit_word(unsigned int id, u32 word)
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{
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void __iomem *io_base;
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omap_mcbsp_word_length word_length;
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if (!omap_mcbsp_check_valid_id(id)) {
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printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
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return;
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}
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io_base = mcbsp[id].io_base;
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word_length = mcbsp[id].tx_word_length;
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wait_for_completion(&(mcbsp[id].tx_irq_completion));
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if (word_length > OMAP_MCBSP_WORD_16)
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OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
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OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
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}
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EXPORT_SYMBOL(omap_mcbsp_xmit_word);
|
|
|
|
u32 omap_mcbsp_recv_word(unsigned int id)
|
|
{
|
|
void __iomem *io_base;
|
|
u16 word_lsb, word_msb = 0;
|
|
omap_mcbsp_word_length word_length;
|
|
|
|
if (!omap_mcbsp_check_valid_id(id)) {
|
|
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
|
return -ENODEV;
|
|
}
|
|
|
|
word_length = mcbsp[id].rx_word_length;
|
|
io_base = mcbsp[id].io_base;
|
|
|
|
wait_for_completion(&(mcbsp[id].rx_irq_completion));
|
|
|
|
if (word_length > OMAP_MCBSP_WORD_16)
|
|
word_msb = OMAP_MCBSP_READ(io_base, DRR2);
|
|
word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
|
|
|
|
return (word_lsb | (word_msb << 16));
|
|
}
|
|
EXPORT_SYMBOL(omap_mcbsp_recv_word);
|
|
|
|
int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
|
|
{
|
|
void __iomem *io_base;
|
|
omap_mcbsp_word_length tx_word_length;
|
|
omap_mcbsp_word_length rx_word_length;
|
|
u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
|
|
|
|
if (!omap_mcbsp_check_valid_id(id)) {
|
|
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
|
return -ENODEV;
|
|
}
|
|
|
|
io_base = mcbsp[id].io_base;
|
|
tx_word_length = mcbsp[id].tx_word_length;
|
|
rx_word_length = mcbsp[id].rx_word_length;
|
|
|
|
if (tx_word_length != rx_word_length)
|
|
return -EINVAL;
|
|
|
|
/* First we wait for the transmitter to be ready */
|
|
spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
|
|
while (!(spcr2 & XRDY)) {
|
|
spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
|
|
if (attempts++ > 1000) {
|
|
/* We must reset the transmitter */
|
|
OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
|
|
udelay(10);
|
|
OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
|
|
udelay(10);
|
|
dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
|
|
"ready\n", mcbsp[id].id);
|
|
return -EAGAIN;
|
|
}
|
|
}
|
|
|
|
/* Now we can push the data */
|
|
if (tx_word_length > OMAP_MCBSP_WORD_16)
|
|
OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
|
|
OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
|
|
|
|
/* We wait for the receiver to be ready */
|
|
spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
|
|
while (!(spcr1 & RRDY)) {
|
|
spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
|
|
if (attempts++ > 1000) {
|
|
/* We must reset the receiver */
|
|
OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
|
|
udelay(10);
|
|
OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
|
|
udelay(10);
|
|
dev_err(mcbsp[id].dev, "McBSP%d receiver not "
|
|
"ready\n", mcbsp[id].id);
|
|
return -EAGAIN;
|
|
}
|
|
}
|
|
|
|
/* Receiver is ready, let's read the dummy data */
|
|
if (rx_word_length > OMAP_MCBSP_WORD_16)
|
|
word_msb = OMAP_MCBSP_READ(io_base, DRR2);
|
|
word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
|
|
|
|
int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
|
|
{
|
|
u32 clock_word = 0;
|
|
void __iomem *io_base;
|
|
omap_mcbsp_word_length tx_word_length;
|
|
omap_mcbsp_word_length rx_word_length;
|
|
u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
|
|
|
|
if (!omap_mcbsp_check_valid_id(id)) {
|
|
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
|
return -ENODEV;
|
|
}
|
|
|
|
io_base = mcbsp[id].io_base;
|
|
tx_word_length = mcbsp[id].tx_word_length;
|
|
rx_word_length = mcbsp[id].rx_word_length;
|
|
|
|
if (tx_word_length != rx_word_length)
|
|
return -EINVAL;
|
|
|
|
/* First we wait for the transmitter to be ready */
|
|
spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
|
|
while (!(spcr2 & XRDY)) {
|
|
spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
|
|
if (attempts++ > 1000) {
|
|
/* We must reset the transmitter */
|
|
OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
|
|
udelay(10);
|
|
OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
|
|
udelay(10);
|
|
dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
|
|
"ready\n", mcbsp[id].id);
|
|
return -EAGAIN;
|
|
}
|
|
}
|
|
|
|
/* We first need to enable the bus clock */
|
|
if (tx_word_length > OMAP_MCBSP_WORD_16)
|
|
OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
|
|
OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
|
|
|
|
/* We wait for the receiver to be ready */
|
|
spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
|
|
while (!(spcr1 & RRDY)) {
|
|
spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
|
|
if (attempts++ > 1000) {
|
|
/* We must reset the receiver */
|
|
OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
|
|
udelay(10);
|
|
OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
|
|
udelay(10);
|
|
dev_err(mcbsp[id].dev, "McBSP%d receiver not "
|
|
"ready\n", mcbsp[id].id);
|
|
return -EAGAIN;
|
|
}
|
|
}
|
|
|
|
/* Receiver is ready, there is something for us */
|
|
if (rx_word_length > OMAP_MCBSP_WORD_16)
|
|
word_msb = OMAP_MCBSP_READ(io_base, DRR2);
|
|
word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
|
|
|
|
word[0] = (word_lsb | (word_msb << 16));
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
|
|
|
|
/*
|
|
* Simple DMA based buffer rx/tx routines.
|
|
* Nothing fancy, just a single buffer tx/rx through DMA.
|
|
* The DMA resources are released once the transfer is done.
|
|
* For anything fancier, you should use your own customized DMA
|
|
* routines and callbacks.
|
|
*/
|
|
int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
|
|
unsigned int length)
|
|
{
|
|
int dma_tx_ch;
|
|
int src_port = 0;
|
|
int dest_port = 0;
|
|
int sync_dev = 0;
|
|
|
|
if (!omap_mcbsp_check_valid_id(id)) {
|
|
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX",
|
|
omap_mcbsp_tx_dma_callback,
|
|
&mcbsp[id],
|
|
&dma_tx_ch)) {
|
|
dev_err(mcbsp[id].dev, " Unable to request DMA channel for "
|
|
"McBSP%d TX. Trying IRQ based TX\n",
|
|
mcbsp[id].id);
|
|
return -EAGAIN;
|
|
}
|
|
mcbsp[id].dma_tx_lch = dma_tx_ch;
|
|
|
|
dev_err(mcbsp[id].dev, "McBSP%d TX DMA on channel %d\n", mcbsp[id].id,
|
|
dma_tx_ch);
|
|
|
|
init_completion(&(mcbsp[id].tx_dma_completion));
|
|
|
|
if (cpu_class_is_omap1()) {
|
|
src_port = OMAP_DMA_PORT_TIPB;
|
|
dest_port = OMAP_DMA_PORT_EMIFF;
|
|
}
|
|
if (cpu_class_is_omap2())
|
|
sync_dev = mcbsp[id].dma_tx_sync;
|
|
|
|
omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
|
|
OMAP_DMA_DATA_TYPE_S16,
|
|
length >> 1, 1,
|
|
OMAP_DMA_SYNC_ELEMENT,
|
|
sync_dev, 0);
|
|
|
|
omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
|
|
src_port,
|
|
OMAP_DMA_AMODE_CONSTANT,
|
|
mcbsp[id].phys_base + OMAP_MCBSP_REG_DXR1,
|
|
0, 0);
|
|
|
|
omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
|
|
dest_port,
|
|
OMAP_DMA_AMODE_POST_INC,
|
|
buffer,
|
|
0, 0);
|
|
|
|
omap_start_dma(mcbsp[id].dma_tx_lch);
|
|
wait_for_completion(&(mcbsp[id].tx_dma_completion));
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
|
|
|
|
int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
|
|
unsigned int length)
|
|
{
|
|
int dma_rx_ch;
|
|
int src_port = 0;
|
|
int dest_port = 0;
|
|
int sync_dev = 0;
|
|
|
|
if (!omap_mcbsp_check_valid_id(id)) {
|
|
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX",
|
|
omap_mcbsp_rx_dma_callback,
|
|
&mcbsp[id],
|
|
&dma_rx_ch)) {
|
|
dev_err(mcbsp[id].dev, "Unable to request DMA channel for "
|
|
"McBSP%d RX. Trying IRQ based RX\n",
|
|
mcbsp[id].id);
|
|
return -EAGAIN;
|
|
}
|
|
mcbsp[id].dma_rx_lch = dma_rx_ch;
|
|
|
|
dev_err(mcbsp[id].dev, "McBSP%d RX DMA on channel %d\n", mcbsp[id].id,
|
|
dma_rx_ch);
|
|
|
|
init_completion(&(mcbsp[id].rx_dma_completion));
|
|
|
|
if (cpu_class_is_omap1()) {
|
|
src_port = OMAP_DMA_PORT_TIPB;
|
|
dest_port = OMAP_DMA_PORT_EMIFF;
|
|
}
|
|
if (cpu_class_is_omap2())
|
|
sync_dev = mcbsp[id].dma_rx_sync;
|
|
|
|
omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
|
|
OMAP_DMA_DATA_TYPE_S16,
|
|
length >> 1, 1,
|
|
OMAP_DMA_SYNC_ELEMENT,
|
|
sync_dev, 0);
|
|
|
|
omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
|
|
src_port,
|
|
OMAP_DMA_AMODE_CONSTANT,
|
|
mcbsp[id].phys_base + OMAP_MCBSP_REG_DRR1,
|
|
0, 0);
|
|
|
|
omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
|
|
dest_port,
|
|
OMAP_DMA_AMODE_POST_INC,
|
|
buffer,
|
|
0, 0);
|
|
|
|
omap_start_dma(mcbsp[id].dma_rx_lch);
|
|
wait_for_completion(&(mcbsp[id].rx_dma_completion));
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
|
|
|
|
/*
|
|
* SPI wrapper.
|
|
* Since SPI setup is much simpler than the generic McBSP one,
|
|
* this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
|
|
* Once this is done, you can call omap_mcbsp_start().
|
|
*/
|
|
void omap_mcbsp_set_spi_mode(unsigned int id,
|
|
const struct omap_mcbsp_spi_cfg *spi_cfg)
|
|
{
|
|
struct omap_mcbsp_reg_cfg mcbsp_cfg;
|
|
|
|
if (!omap_mcbsp_check_valid_id(id)) {
|
|
printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
|
|
return;
|
|
}
|
|
|
|
memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
|
|
|
|
/* SPI has only one frame */
|
|
mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
|
|
mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
|
|
|
|
/* Clock stop mode */
|
|
if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
|
|
mcbsp_cfg.spcr1 |= (1 << 12);
|
|
else
|
|
mcbsp_cfg.spcr1 |= (3 << 11);
|
|
|
|
/* Set clock parities */
|
|
if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
|
|
mcbsp_cfg.pcr0 |= CLKRP;
|
|
else
|
|
mcbsp_cfg.pcr0 &= ~CLKRP;
|
|
|
|
if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
|
|
mcbsp_cfg.pcr0 &= ~CLKXP;
|
|
else
|
|
mcbsp_cfg.pcr0 |= CLKXP;
|
|
|
|
/* Set SCLKME to 0 and CLKSM to 1 */
|
|
mcbsp_cfg.pcr0 &= ~SCLKME;
|
|
mcbsp_cfg.srgr2 |= CLKSM;
|
|
|
|
/* Set FSXP */
|
|
if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
|
|
mcbsp_cfg.pcr0 &= ~FSXP;
|
|
else
|
|
mcbsp_cfg.pcr0 |= FSXP;
|
|
|
|
if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
|
|
mcbsp_cfg.pcr0 |= CLKXM;
|
|
mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
|
|
mcbsp_cfg.pcr0 |= FSXM;
|
|
mcbsp_cfg.srgr2 &= ~FSGM;
|
|
mcbsp_cfg.xcr2 |= XDATDLY(1);
|
|
mcbsp_cfg.rcr2 |= RDATDLY(1);
|
|
} else {
|
|
mcbsp_cfg.pcr0 &= ~CLKXM;
|
|
mcbsp_cfg.srgr1 |= CLKGDV(1);
|
|
mcbsp_cfg.pcr0 &= ~FSXM;
|
|
mcbsp_cfg.xcr2 &= ~XDATDLY(3);
|
|
mcbsp_cfg.rcr2 &= ~RDATDLY(3);
|
|
}
|
|
|
|
mcbsp_cfg.xcr2 &= ~XPHASE;
|
|
mcbsp_cfg.rcr2 &= ~RPHASE;
|
|
|
|
omap_mcbsp_config(id, &mcbsp_cfg);
|
|
}
|
|
EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
|
|
|
|
/*
|
|
* McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
|
|
* 730 has only 2 McBSP, and both of them are MPU peripherals.
|
|
*/
|
|
static int __init omap_mcbsp_probe(struct platform_device *pdev)
|
|
{
|
|
struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
|
|
int id = pdev->id - 1;
|
|
int ret = 0;
|
|
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "McBSP device initialized without"
|
|
"platform data\n");
|
|
ret = -EINVAL;
|
|
goto exit;
|
|
}
|
|
|
|
dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
|
|
|
|
if (id >= OMAP_MAX_MCBSP_COUNT) {
|
|
dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
|
|
ret = -EINVAL;
|
|
goto exit;
|
|
}
|
|
|
|
spin_lock_init(&mcbsp[id].lock);
|
|
mcbsp[id].id = id + 1;
|
|
mcbsp[id].free = 1;
|
|
mcbsp[id].dma_tx_lch = -1;
|
|
mcbsp[id].dma_rx_lch = -1;
|
|
|
|
mcbsp[id].phys_base = pdata->phys_base;
|
|
mcbsp[id].io_base = ioremap(pdata->phys_base, SZ_4K);
|
|
if (!mcbsp[id].io_base) {
|
|
ret = -ENOMEM;
|
|
goto err_ioremap;
|
|
}
|
|
|
|
/* Default I/O is IRQ based */
|
|
mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;
|
|
mcbsp[id].tx_irq = pdata->tx_irq;
|
|
mcbsp[id].rx_irq = pdata->rx_irq;
|
|
mcbsp[id].dma_rx_sync = pdata->dma_rx_sync;
|
|
mcbsp[id].dma_tx_sync = pdata->dma_tx_sync;
|
|
|
|
if (pdata->clk_name)
|
|
mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name);
|
|
if (IS_ERR(mcbsp[id].clk)) {
|
|
dev_err(&pdev->dev,
|
|
"Invalid clock configuration for McBSP%d.\n",
|
|
mcbsp[id].id);
|
|
ret = PTR_ERR(mcbsp[id].clk);
|
|
goto err_clk;
|
|
}
|
|
|
|
mcbsp[id].pdata = pdata;
|
|
mcbsp[id].dev = &pdev->dev;
|
|
platform_set_drvdata(pdev, &mcbsp[id]);
|
|
return 0;
|
|
|
|
err_clk:
|
|
iounmap(mcbsp[id].io_base);
|
|
err_ioremap:
|
|
mcbsp[id].free = 0;
|
|
exit:
|
|
return ret;
|
|
}
|
|
|
|
static int omap_mcbsp_remove(struct platform_device *pdev)
|
|
{
|
|
struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
if (mcbsp) {
|
|
|
|
if (mcbsp->pdata && mcbsp->pdata->ops &&
|
|
mcbsp->pdata->ops->free)
|
|
mcbsp->pdata->ops->free(mcbsp->id);
|
|
|
|
clk_disable(mcbsp->clk);
|
|
clk_put(mcbsp->clk);
|
|
|
|
iounmap(mcbsp->io_base);
|
|
|
|
mcbsp->clk = NULL;
|
|
mcbsp->free = 0;
|
|
mcbsp->dev = NULL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver omap_mcbsp_driver = {
|
|
.probe = omap_mcbsp_probe,
|
|
.remove = omap_mcbsp_remove,
|
|
.driver = {
|
|
.name = "omap-mcbsp",
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},
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};
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|
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int __init omap_mcbsp_init(void)
|
|
{
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|
/* Register the McBSP driver */
|
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return platform_driver_register(&omap_mcbsp_driver);
|
|
}
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|