638b266630
Patch from Marc Singer Updates to the lpd7a40x_platform files. Includes support for new architecture, lpd7a400. Signed-off-by: Marc Singer <elf@buici.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
173 lines
4.1 KiB
C
173 lines
4.1 KiB
C
/* arch/arm/mach-lh7a40x/irq-lh7a404.c
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*
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* Copyright (C) 2004 Logic Product Development
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/irqs.h>
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#include "common.h"
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#define USE_PRIORITIES
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/* See Documentation/arm/Sharp-LH/VectoredInterruptController for more
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* information on using the vectored interrupt controller's
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* prioritizing feature. */
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static unsigned char irq_pri_vic1[] = {
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#if defined (USE_PRIORITIES)
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IRQ_GPIO3INTR, /* CPLD */
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IRQ_DMAM2P4, IRQ_DMAM2P5, /* AC97 */
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#endif
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};
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static unsigned char irq_pri_vic2[] = {
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#if defined (USE_PRIORITIES)
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IRQ_T3UI, /* Timer */
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IRQ_GPIO7INTR, /* CPLD */
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IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR,
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IRQ_LCDINTR, /* LCD */
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IRQ_TSCINTR, /* ADC/Touchscreen */
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#endif
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};
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/* CPU IRQ handling */
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static void lh7a404_vic1_mask_irq (u32 irq)
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{
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VIC1_INTENCLR = (1 << irq);
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}
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static void lh7a404_vic1_unmask_irq (u32 irq)
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{
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VIC1_INTEN = (1 << irq);
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}
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static void lh7a404_vic2_mask_irq (u32 irq)
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{
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VIC2_INTENCLR = (1 << (irq - 32));
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}
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static void lh7a404_vic2_unmask_irq (u32 irq)
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{
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VIC2_INTEN = (1 << (irq - 32));
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}
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static void lh7a404_vic1_ack_gpio_irq (u32 irq)
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{
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GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
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VIC1_INTENCLR = (1 << irq);
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}
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static void lh7a404_vic2_ack_gpio_irq (u32 irq)
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{
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GPIO_GPIOFEOI = (1 << IRQ_TO_GPIO (irq));
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VIC2_INTENCLR = (1 << irq);
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}
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static struct irqchip lh7a404_vic1_chip = {
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.ack = lh7a404_vic1_mask_irq, /* Because level-triggered */
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.mask = lh7a404_vic1_mask_irq,
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.unmask = lh7a404_vic1_unmask_irq,
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};
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static struct irqchip lh7a404_vic2_chip = {
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.ack = lh7a404_vic2_mask_irq, /* Because level-triggered */
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.mask = lh7a404_vic2_mask_irq,
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.unmask = lh7a404_vic2_unmask_irq,
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};
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static struct irqchip lh7a404_gpio_vic1_chip = {
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.ack = lh7a404_vic1_ack_gpio_irq,
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.mask = lh7a404_vic1_mask_irq,
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.unmask = lh7a404_vic1_unmask_irq,
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};
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static struct irqchip lh7a404_gpio_vic2_chip = {
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.ack = lh7a404_vic2_ack_gpio_irq,
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.mask = lh7a404_vic2_mask_irq,
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.unmask = lh7a404_vic2_unmask_irq,
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};
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/* IRQ initialization */
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#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
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extern void* branch_irq_lh7a400;
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#endif
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void __init lh7a404_init_irq (void)
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{
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int irq;
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#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
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#define NOP 0xe1a00000 /* mov r0, r0 */
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branch_irq_lh7a400 = NOP;
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#endif
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VIC1_INTENCLR = 0xffffffff;
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VIC2_INTENCLR = 0xffffffff;
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VIC1_INTSEL = 0; /* All IRQs */
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VIC2_INTSEL = 0; /* All IRQs */
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VIC1_NVADDR = VA_VIC1DEFAULT;
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VIC2_NVADDR = VA_VIC2DEFAULT;
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VIC1_VECTADDR = 0;
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VIC2_VECTADDR = 0;
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GPIO_GPIOFINTEN = 0x00; /* Disable all GPIOF interrupts */
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barrier ();
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/* Install prioritized interrupts, if there are any. */
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/* The | 0x20*/
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for (irq = 0; irq < 16; ++irq) {
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(&VIC1_VAD0)[irq]
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= (irq < ARRAY_SIZE (irq_pri_vic1))
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? (irq_pri_vic1[irq] | VA_VECTORED) : 0;
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(&VIC1_VECTCNTL0)[irq]
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= (irq < ARRAY_SIZE (irq_pri_vic1))
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? (irq_pri_vic1[irq] | VIC_CNTL_ENABLE) : 0;
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(&VIC2_VAD0)[irq]
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= (irq < ARRAY_SIZE (irq_pri_vic2))
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? (irq_pri_vic2[irq] | VA_VECTORED) : 0;
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(&VIC2_VECTCNTL0)[irq]
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= (irq < ARRAY_SIZE (irq_pri_vic2))
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? (irq_pri_vic2[irq] | VIC_CNTL_ENABLE) : 0;
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}
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for (irq = 0; irq < NR_IRQS; ++irq) {
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switch (irq) {
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case IRQ_GPIO0INTR:
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case IRQ_GPIO1INTR:
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case IRQ_GPIO2INTR:
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case IRQ_GPIO3INTR:
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case IRQ_GPIO4INTR:
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case IRQ_GPIO5INTR:
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case IRQ_GPIO6INTR:
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case IRQ_GPIO7INTR:
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set_irq_chip (irq, irq < 32
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? &lh7a404_gpio_vic1_chip
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: &lh7a404_gpio_vic2_chip);
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set_irq_handler (irq, do_level_IRQ); /* OK default */
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break;
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default:
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set_irq_chip (irq, irq < 32
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? &lh7a404_vic1_chip
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: &lh7a404_vic2_chip);
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set_irq_handler (irq, do_level_IRQ);
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}
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set_irq_flags (irq, IRQF_VALID);
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}
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lh7a40x_init_board_irq ();
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}
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