75540c1ac3
Patch mainly from Eric Miao, with minor edits by rmk. Note: PWM0 and PWM2 share the same register I/O space and clock gating on pxa{27x, 3xx}, thus PWM2 is treated in the driver as a child PWM of PWM0. And this is also true for PWM1/3. Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
320 lines
7.7 KiB
C
320 lines
7.7 KiB
C
/*
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* linux/arch/arm/mach-pxa/pxa25x.c
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* Code specific to PXA21x/25x/26x variants.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Since this file should be linked before any other machine specific file,
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* the __initcall() here will be executed first. This serves as default
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* initialization stuff for PXA machines which can be overridden later if
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* need be.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/suspend.h>
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#include <linux/sysdev.h>
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#include <asm/hardware.h>
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#include <asm/arch/irqs.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/mfp-pxa25x.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/dma.h>
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#include "generic.h"
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#include "devices.h"
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#include "clock.h"
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/*
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* Various clock factors driven by the CCCR register.
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*/
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/* Crystal Frequency to Memory Frequency Multiplier (L) */
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static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
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/* Memory Frequency to Run Mode Frequency Multiplier (M) */
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static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
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/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
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/* Note: we store the value N * 2 here. */
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static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
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/* Crystal clock */
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#define BASE_CLK 3686400
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/*
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* Get the clock frequency as reflected by CCCR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa25x_get_clk_frequency_khz(int info)
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{
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unsigned long cccr, turbo;
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unsigned int l, L, m, M, n2, N;
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cccr = CCCR;
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
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l = L_clk_mult[(cccr >> 0) & 0x1f];
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m = M_clk_mult[(cccr >> 5) & 0x03];
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n2 = N2_clk_mult[(cccr >> 7) & 0x07];
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L = l * BASE_CLK;
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M = m * L;
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N = n2 * M / 2;
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if(info)
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{
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L += 5000;
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printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
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L / 1000000, (L % 1000000) / 10000, l );
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M += 5000;
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printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
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M / 1000000, (M % 1000000) / 10000, m );
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N += 5000;
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printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
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N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
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(turbo & 1) ? "" : "in" );
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}
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return (turbo & 1) ? (N/1000) : (M/1000);
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}
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/*
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* Return the current memory clock frequency in units of 10kHz
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*/
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unsigned int pxa25x_get_memclk_frequency_10khz(void)
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{
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return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
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}
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static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
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{
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return pxa25x_get_memclk_frequency_10khz() * 10000;
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}
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static const struct clkops clk_pxa25x_lcd_ops = {
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.enable = clk_cken_enable,
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.disable = clk_cken_disable,
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.getrate = clk_pxa25x_lcd_getrate,
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};
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/*
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* 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
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* 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
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* 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
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*/
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static struct clk pxa25x_hwuart_clk =
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INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
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;
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static struct clk pxa25x_clks[] = {
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INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
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INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
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INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
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INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
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INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
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INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
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INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
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INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev),
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INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
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INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
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INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev),
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INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev),
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INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
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/*
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INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
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*/
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INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
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};
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#ifdef CONFIG_PM
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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/*
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* List of global PXA peripheral registers to preserve.
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
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SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
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SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
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SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_CKEN,
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SLEEP_SAVE_COUNT
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};
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static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
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{
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SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
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SAVE(GAFR0_L); SAVE(GAFR0_U);
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SAVE(GAFR1_L); SAVE(GAFR1_U);
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SAVE(GAFR2_L); SAVE(GAFR2_U);
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SAVE(CKEN);
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SAVE(PSTR);
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/* Clear GPIO transition detect bits */
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GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
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}
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static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
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{
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/* ensure not to come back here if it wasn't intended */
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PSPR = 0;
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/* restore registers */
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RESTORE(GAFR0_L); RESTORE(GAFR0_U);
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RESTORE(GAFR1_L); RESTORE(GAFR1_U);
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RESTORE(GAFR2_L); RESTORE(GAFR2_U);
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RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
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PSSR = PSSR_RDH | PSSR_PH;
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RESTORE(CKEN);
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RESTORE(PSTR);
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}
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static void pxa25x_cpu_pm_enter(suspend_state_t state)
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{
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/* Clear reset status */
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RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
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switch (state) {
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case PM_SUSPEND_MEM:
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/* set resume return address */
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PSPR = virt_to_phys(pxa_cpu_resume);
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pxa25x_cpu_suspend(PWRMODE_SLEEP);
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break;
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}
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}
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static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
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.save_count = SLEEP_SAVE_COUNT,
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.valid = suspend_valid_only_mem,
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.save = pxa25x_cpu_pm_save,
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.restore = pxa25x_cpu_pm_restore,
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.enter = pxa25x_cpu_pm_enter,
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};
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static void __init pxa25x_init_pm(void)
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{
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pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
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}
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#else
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static inline void pxa25x_init_pm(void) {}
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#endif
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/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
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*/
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static int pxa25x_set_wake(unsigned int irq, unsigned int on)
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{
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int gpio = IRQ_TO_GPIO(irq);
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uint32_t mask = 0;
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if (gpio >= 0 && gpio < 85)
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return gpio_set_wake(gpio, on);
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if (irq == IRQ_RTCAlrm) {
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mask = PWER_RTC;
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goto set_pwer;
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}
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return -EINVAL;
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set_pwer:
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if (on)
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PWER |= mask;
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else
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PWER &=~mask;
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return 0;
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}
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void __init pxa25x_init_irq(void)
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{
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pxa_init_irq(32, pxa25x_set_wake);
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pxa_init_gpio(85, pxa25x_set_wake);
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}
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static struct platform_device *pxa25x_devices[] __initdata = {
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&pxa_device_udc,
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&pxa_device_ffuart,
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&pxa_device_btuart,
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&pxa_device_stuart,
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&pxa_device_i2s,
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&pxa_device_rtc,
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&pxa25x_device_ssp,
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&pxa25x_device_nssp,
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&pxa25x_device_assp,
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&pxa25x_device_pwm0,
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&pxa25x_device_pwm1,
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};
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static struct sys_device pxa25x_sysdev[] = {
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{
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.cls = &pxa_irq_sysclass,
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}, {
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.cls = &pxa_gpio_sysclass,
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},
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};
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static int __init pxa25x_init(void)
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{
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int i, ret = 0;
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/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
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if (cpu_is_pxa25x())
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clks_register(&pxa25x_hwuart_clk, 1);
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if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
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clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
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if ((ret = pxa_init_dma(16)))
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return ret;
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pxa25x_init_pm();
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for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
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ret = sysdev_register(&pxa25x_sysdev[i]);
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if (ret)
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pr_err("failed to register sysdev[%d]\n", i);
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}
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ret = platform_add_devices(pxa25x_devices,
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ARRAY_SIZE(pxa25x_devices));
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if (ret)
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return ret;
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}
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/* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
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if (cpu_is_pxa25x())
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ret = platform_device_register(&pxa_device_hwuart);
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return ret;
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}
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postcore_initcall(pxa25x_init);
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