8051effcbc
This patch is V2 of SPI Master support for the SuperH MSIOF. Full duplex, spi mode 0-3, active high cs, 3-wire and lsb first should all be supported, but the driver has so far only been tested with "mmc_spi". The MSIOF hardware comes with 32-bit FIFOs for receive and transmit, and this driver simply breaks the SPI messages into FIFO-sized chunks. The MSIOF hardware manages the pins for clock, receive and transmit (sck/miso/mosi), but the chip select pin is managed by software and must be configured as a regular GPIO pin by the board code. Performance wise there is still room for improvement, but on a Ecovec board with the built-in sh7724 MSIOF0 this driver gets Mini-sd read speeds of about half a megabyte per second. Future work include better clock setup and merging of 8-bit transfers into 32-bit words to reduce interrupt load and improve throughput. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
11 lines
185 B
C
11 lines
185 B
C
#ifndef __SPI_SH_MSIOF_H__
|
|
#define __SPI_SH_MSIOF_H__
|
|
|
|
struct sh_msiof_spi_info {
|
|
int tx_fifo_override;
|
|
int rx_fifo_override;
|
|
u16 num_chipselect;
|
|
};
|
|
|
|
#endif /* __SPI_SH_MSIOF_H__ */
|