4d22de3e6c
This driver is required by the Chelsio T3 RDMA driver posted by Steve Wise. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
166 lines
2.8 KiB
C
166 lines
2.8 KiB
C
/*
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* This file is part of the Chelsio T3 Ethernet driver for Linux.
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*
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* Copyright (C) 2003-2006 Chelsio Communications. All rights reserved.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
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* release for licensing terms and conditions.
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*/
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#ifndef __CHIOCTL_H__
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#define __CHIOCTL_H__
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/*
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* Ioctl commands specific to this driver.
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*/
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enum {
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CHELSIO_SETREG = 1024,
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CHELSIO_GETREG,
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CHELSIO_SETTPI,
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CHELSIO_GETTPI,
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CHELSIO_GETMTUTAB,
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CHELSIO_SETMTUTAB,
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CHELSIO_GETMTU,
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CHELSIO_SET_PM,
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CHELSIO_GET_PM,
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CHELSIO_GET_TCAM,
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CHELSIO_SET_TCAM,
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CHELSIO_GET_TCB,
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CHELSIO_GET_MEM,
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CHELSIO_LOAD_FW,
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CHELSIO_GET_PROTO,
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CHELSIO_SET_PROTO,
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CHELSIO_SET_TRACE_FILTER,
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CHELSIO_SET_QSET_PARAMS,
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CHELSIO_GET_QSET_PARAMS,
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CHELSIO_SET_QSET_NUM,
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CHELSIO_GET_QSET_NUM,
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CHELSIO_SET_PKTSCHED,
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};
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struct ch_reg {
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uint32_t cmd;
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uint32_t addr;
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uint32_t val;
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};
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struct ch_cntxt {
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uint32_t cmd;
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uint32_t cntxt_type;
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uint32_t cntxt_id;
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uint32_t data[4];
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};
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/* context types */
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enum { CNTXT_TYPE_EGRESS, CNTXT_TYPE_FL, CNTXT_TYPE_RSP, CNTXT_TYPE_CQ };
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struct ch_desc {
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uint32_t cmd;
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uint32_t queue_num;
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uint32_t idx;
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uint32_t size;
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uint8_t data[128];
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};
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struct ch_mem_range {
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uint32_t cmd;
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uint32_t mem_id;
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uint32_t addr;
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uint32_t len;
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uint32_t version;
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uint8_t buf[0];
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};
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struct ch_qset_params {
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uint32_t cmd;
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uint32_t qset_idx;
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int32_t txq_size[3];
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int32_t rspq_size;
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int32_t fl_size[2];
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int32_t intr_lat;
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int32_t polling;
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int32_t cong_thres;
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};
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struct ch_pktsched_params {
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uint32_t cmd;
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uint8_t sched;
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uint8_t idx;
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uint8_t min;
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uint8_t max;
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uint8_t binding;
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};
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#ifndef TCB_SIZE
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# define TCB_SIZE 128
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#endif
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/* TCB size in 32-bit words */
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#define TCB_WORDS (TCB_SIZE / 4)
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enum { MEM_CM, MEM_PMRX, MEM_PMTX }; /* ch_mem_range.mem_id values */
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struct ch_mtus {
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uint32_t cmd;
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uint32_t nmtus;
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uint16_t mtus[NMTUS];
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};
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struct ch_pm {
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uint32_t cmd;
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uint32_t tx_pg_sz;
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uint32_t tx_num_pg;
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uint32_t rx_pg_sz;
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uint32_t rx_num_pg;
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uint32_t pm_total;
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};
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struct ch_tcam {
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uint32_t cmd;
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uint32_t tcam_size;
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uint32_t nservers;
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uint32_t nroutes;
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uint32_t nfilters;
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};
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struct ch_tcb {
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uint32_t cmd;
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uint32_t tcb_index;
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uint32_t tcb_data[TCB_WORDS];
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};
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struct ch_tcam_word {
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uint32_t cmd;
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uint32_t addr;
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uint32_t buf[3];
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};
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struct ch_trace {
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uint32_t cmd;
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uint32_t sip;
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uint32_t sip_mask;
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uint32_t dip;
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uint32_t dip_mask;
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uint16_t sport;
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uint16_t sport_mask;
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uint16_t dport;
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uint16_t dport_mask;
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uint32_t vlan:12;
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uint32_t vlan_mask:12;
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uint32_t intf:4;
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uint32_t intf_mask:4;
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uint8_t proto;
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uint8_t proto_mask;
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uint8_t invert_match:1;
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uint8_t config_tx:1;
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uint8_t config_rx:1;
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uint8_t trace_tx:1;
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uint8_t trace_rx:1;
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};
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#define SIOCCHIOCTL SIOCDEVPRIVATE
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#endif
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