d0a533b182
This patch allows a timer-based delay implementation to be selected by switching the delay routines over to use get_cycles, which is implemented in terms of read_current_timer. This further allows us to skip the loop calibration and have a consistent delay function in the face of core frequency scaling. To avoid the pain of dealing with memory-mapped counters, this implementation uses the co-processor interface to the architected timers when they are available. The previous loop-based implementation is kept around for CPUs without the architected timers and we retain both the maximum delay (2ms) and the corresponding conversion factors for determining the number of loops required for a given interval. Since the indirection of the timer routines will only work when called from C, the sa1100 sleep routines are modified to branch to the loop-based delay functions directly. Tested-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
144 lines
2.8 KiB
ArmAsm
144 lines
2.8 KiB
ArmAsm
/*
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* SA11x0 Assembler Sleep/WakeUp Management Routines
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*
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* Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License.
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*
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* History:
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*
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* 2001-02-06: Cliff Brake Initial code
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*
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* 2001-08-29: Nicolas Pitre Simplified.
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*
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* 2002-05-27: Nicolas Pitre Revisited, more cleanup and simplification.
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* Storage is on the stack now.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/hardware.h>
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.text
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/*
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* sa1100_finish_suspend()
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*
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* Causes sa11x0 to enter sleep state
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*
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* Must be aligned to a cacheline.
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*/
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.balign 32
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ENTRY(sa1100_finish_suspend)
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@ disable clock switching
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mcr p15, 0, r1, c15, c2, 2
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ldr r6, =MDREFR
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ldr r4, [r6]
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orr r4, r4, #MDREFR_K1DB2
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ldr r5, =PPCR
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@ Pre-load __loop_udelay into the I-cache
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mov r0, #1
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bl __loop_udelay
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mov r0, r0
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@ The following must all exist in a single cache line to
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@ avoid accessing memory until this sequence is complete,
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@ otherwise we occasionally hang.
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@ Adjust memory timing before lowering CPU clock
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str r4, [r6]
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@ delay 90us and set CPU PLL to lowest speed
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@ fixes resume problem on high speed SA1110
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mov r0, #90
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bl __loop_udelay
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mov r1, #0
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str r1, [r5]
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mov r0, #90
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bl __loop_udelay
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/*
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* SA1110 SDRAM controller workaround. register values:
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*
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* r0 = &MSC0
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* r1 = &MSC1
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* r2 = &MSC2
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* r3 = MSC0 value
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* r4 = MSC1 value
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* r5 = MSC2 value
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* r6 = &MDREFR
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* r7 = first MDREFR value
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* r8 = second MDREFR value
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* r9 = &MDCNFG
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* r10 = MDCNFG value
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* r11 = third MDREFR value
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* r12 = &PMCR
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* r13 = PMCR value (1)
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*/
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ldr r0, =MSC0
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ldr r1, =MSC1
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ldr r2, =MSC2
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ldr r3, [r0]
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bic r3, r3, #FMsk(MSC_RT)
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bic r3, r3, #FMsk(MSC_RT)<<16
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ldr r4, [r1]
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bic r4, r4, #FMsk(MSC_RT)
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bic r4, r4, #FMsk(MSC_RT)<<16
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ldr r5, [r2]
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bic r5, r5, #FMsk(MSC_RT)
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bic r5, r5, #FMsk(MSC_RT)<<16
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ldr r7, [r6]
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bic r7, r7, #0x0000FF00
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bic r7, r7, #0x000000F0
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orr r8, r7, #MDREFR_SLFRSH
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ldr r9, =MDCNFG
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ldr r10, [r9]
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bic r10, r10, #(MDCNFG_DE0+MDCNFG_DE1)
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bic r10, r10, #(MDCNFG_DE2+MDCNFG_DE3)
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bic r11, r8, #MDREFR_SLFRSH
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bic r11, r11, #MDREFR_E1PIN
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ldr r12, =PMCR
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mov r13, #PMCR_SF
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b sa1110_sdram_controller_fix
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.align 5
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sa1110_sdram_controller_fix:
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@ Step 1 clear RT field of all MSCx registers
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str r3, [r0]
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str r4, [r1]
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str r5, [r2]
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@ Step 2 clear DRI field in MDREFR
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str r7, [r6]
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@ Step 3 set SLFRSH bit in MDREFR
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str r8, [r6]
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@ Step 4 clear DE bis in MDCNFG
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str r10, [r9]
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@ Step 5 clear DRAM refresh control register
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str r11, [r6]
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@ Wow, now the hardware suspend request pins can be used, that makes them functional for
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@ about 7 ns out of the entire time that the CPU is running!
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@ Step 6 set force sleep bit in PMCR
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str r13, [r12]
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20: b 20b @ loop waiting for sleep
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