77d4309e19
Only external interrupts in edge detect mode support ack operation. Therefore, in most cases ack is not needed. The patch makes ipic ack only when it's needed. This could boost over all system performance. Signed-off-by: Li Yang <leoli@freescale.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
61 lines
1.5 KiB
C
61 lines
1.5 KiB
C
/*
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* IPIC private definitions and structure.
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*
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* Maintainer: Kumar Gala <galak@kernel.crashing.org>
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*
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* Copyright 2005 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __IPIC_H__
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#define __IPIC_H__
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#include <asm/ipic.h>
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#define NR_IPIC_INTS 128
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/* External IRQS */
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#define IPIC_IRQ_EXT0 48
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#define IPIC_IRQ_EXT1 17
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#define IPIC_IRQ_EXT7 23
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/* Default Priority Registers */
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#define IPIC_PRIORITY_DEFAULT 0x05309770
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/* System Global Interrupt Configuration Register */
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#define SICFR_IPSA 0x00010000
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#define SICFR_IPSB 0x00020000
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#define SICFR_IPSC 0x00040000
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#define SICFR_IPSD 0x00080000
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#define SICFR_MPSA 0x00200000
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#define SICFR_MPSB 0x00400000
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/* System External Interrupt Mask Register */
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#define SEMSR_SIRQ0 0x00008000
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/* System Error Control Register */
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#define SERCR_MCPR 0x00000001
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struct ipic {
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volatile u32 __iomem *regs;
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/* The remapper for this IPIC */
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struct irq_host *irqhost;
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};
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struct ipic_info {
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u8 ack; /* pending register offset from base if the irq
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supports ack operation */
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u8 mask; /* mask register offset from base */
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u8 prio; /* priority register offset from base */
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u8 force; /* force register offset from base */
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u8 bit; /* register bit position (as per doc)
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bit mask = 1 << (31 - bit) */
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u8 prio_mask; /* priority mask value */
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};
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#endif /* __IPIC_H__ */
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