a337e44c28
Demura block of dpu will use the register dma path for programming. Change updates the register dma frame-work to allow programming of the demura block. Change-Id: Ie5a64df1b2fffcb84d9554e5211249892ed2d96d Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
226 lines
6.2 KiB
C
226 lines
6.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_HW_UTIL_H
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#define _SDE_HW_UTIL_H
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "sde_hw_mdss.h"
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#include "sde_hw_catalog.h"
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#define REG_MASK(n) ((BIT(n)) - 1)
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#define REG_MASK_SHIFT(n, shift) ((REG_MASK(n)) << (shift))
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#define LP_DDR4_TYPE 0x7
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struct sde_format_extended;
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/*
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* This is the common struct maintained by each sub block
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* for mapping the register offsets in this block to the
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* absoulute IO address
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* @base_off: mdp register mapped offset
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* @blk_off: pipe offset relative to mdss offset
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* @length length of register block offset
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* @xin_id xin id
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* @hwversion mdss hw version number
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*/
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struct sde_hw_blk_reg_map {
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void __iomem *base_off;
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u32 blk_off;
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u32 length;
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u32 xin_id;
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u32 hwversion;
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u32 log_mask;
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};
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/**
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* struct sde_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
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* @enable: detail enhancer enable/disable
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* @sharpen_level1: sharpening strength for noise
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* @sharpen_level2: sharpening strength for signal
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* @ clip: clip shift
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* @ limit: limit value
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* @ thr_quiet: quiet threshold
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* @ thr_dieout: dieout threshold
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* @ thr_high: low threshold
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* @ thr_high: high threshold
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* @ prec_shift: precision shift
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* @ adjust_a: A-coefficients for mapping curve
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* @ adjust_b: B-coefficients for mapping curve
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* @ adjust_c: C-coefficients for mapping curve
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* @ blend: Unsharp Blend Filter Ratio
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*/
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struct sde_hw_scaler3_de_cfg {
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u32 enable;
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int16_t sharpen_level1;
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int16_t sharpen_level2;
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uint16_t clip;
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uint16_t limit;
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uint16_t thr_quiet;
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uint16_t thr_dieout;
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uint16_t thr_low;
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uint16_t thr_high;
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uint16_t prec_shift;
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int16_t adjust_a[SDE_MAX_DE_CURVES];
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int16_t adjust_b[SDE_MAX_DE_CURVES];
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int16_t adjust_c[SDE_MAX_DE_CURVES];
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uint32_t blend;
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};
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/**
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* struct sde_hw_scaler3_cfg : QSEEDv3 configuration
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* @enable: scaler enable
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* @dir_en: direction detection block enable
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* @ init_phase_x: horizontal initial phase
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* @ phase_step_x: horizontal phase step
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* @ init_phase_y: vertical initial phase
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* @ phase_step_y: vertical phase step
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* @ preload_x: horizontal preload value
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* @ preload_y: vertical preload value
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* @ src_width: source width
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* @ src_height: source height
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* @ dst_width: destination width
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* @ dst_height: destination height
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* @ y_rgb_filter_cfg: y/rgb plane filter configuration
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* @ uv_filter_cfg: uv plane filter configuration
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* @ alpha_filter_cfg: alpha filter configuration
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* @ blend_cfg: blend coefficients configuration
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* @ lut_flag: scaler LUT update flags
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* 0x1 swap LUT bank
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* 0x2 update 2D filter LUT
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* 0x4 update y circular filter LUT
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* 0x8 update uv circular filter LUT
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* 0x10 update y separable filter LUT
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* 0x20 update uv separable filter LUT
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* @ dir_lut_idx: 2D filter LUT index
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* @ y_rgb_cir_lut_idx: y circular filter LUT index
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* @ uv_cir_lut_idx: uv circular filter LUT index
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* @ y_rgb_sep_lut_idx: y circular filter LUT index
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* @ uv_sep_lut_idx: uv separable filter LUT index
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* @ dir_lut: pointer to 2D LUT
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* @ cir_lut: pointer to circular filter LUT
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* @ sep_lut: pointer to separable filter LUT
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* @ de: detail enhancer configuration
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* @ dir_weight: Directional Weight
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* @dyn_exp_disabled: Dynamic expansion disabled
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*/
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struct sde_hw_scaler3_cfg {
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u32 enable;
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u32 dir_en;
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int32_t init_phase_x[SDE_MAX_PLANES];
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int32_t phase_step_x[SDE_MAX_PLANES];
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int32_t init_phase_y[SDE_MAX_PLANES];
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int32_t phase_step_y[SDE_MAX_PLANES];
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u32 preload_x[SDE_MAX_PLANES];
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u32 preload_y[SDE_MAX_PLANES];
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u32 src_width[SDE_MAX_PLANES];
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u32 src_height[SDE_MAX_PLANES];
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u32 dst_width;
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u32 dst_height;
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u32 y_rgb_filter_cfg;
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u32 uv_filter_cfg;
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u32 alpha_filter_cfg;
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u32 blend_cfg;
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u32 lut_flag;
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u32 dir_lut_idx;
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u32 y_rgb_cir_lut_idx;
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u32 uv_cir_lut_idx;
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u32 y_rgb_sep_lut_idx;
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u32 uv_sep_lut_idx;
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u32 *dir_lut;
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size_t dir_len;
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u32 *cir_lut;
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size_t cir_len;
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u32 *sep_lut;
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size_t sep_len;
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/*
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* Detail enhancer settings
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*/
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struct sde_hw_scaler3_de_cfg de;
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uint32_t dir_weight;
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uint32_t dyn_exp_disabled;
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};
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struct sde_hw_scaler3_lut_cfg {
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bool is_configured;
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u32 *dir_lut;
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size_t dir_len;
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u32 *cir_lut;
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size_t cir_len;
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u32 *sep_lut;
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size_t sep_len;
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};
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struct sde_hw_inline_pre_downscale_cfg {
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u32 pre_downscale_x_0;
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u32 pre_downscale_x_1;
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u32 pre_downscale_y_0;
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u32 pre_downscale_y_1;
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};
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u32 *sde_hw_util_get_log_mask_ptr(void);
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void sde_reg_write(struct sde_hw_blk_reg_map *c,
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u32 reg_off,
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u32 val,
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const char *name);
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int sde_reg_read(struct sde_hw_blk_reg_map *c, u32 reg_off);
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#define SDE_REG_WRITE(c, off, val) sde_reg_write(c, off, val, #off)
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#define SDE_REG_READ(c, off) sde_reg_read(c, off)
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#define MISR_FRAME_COUNT_MASK 0xFF
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#define MISR_CTRL_ENABLE BIT(8)
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#define MISR_CTRL_STATUS BIT(9)
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#define MISR_CTRL_STATUS_CLEAR BIT(10)
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#define INTF_MISR_CTRL_FREE_RUN_MASK BIT(31)
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#define INTF_MISR_CTRL_INPUT_SEL_DATA BIT(24)
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void *sde_hw_util_get_dir(void);
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void sde_init_scaler_blk(struct sde_scaler_blk *blk, u32 version);
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void sde_set_scaler_v2(struct sde_hw_scaler3_cfg *cfg,
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const struct sde_drm_scaler_v2 *scale_v2);
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void sde_hw_setup_scaler3(struct sde_hw_blk_reg_map *c,
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struct sde_hw_scaler3_cfg *scaler3_cfg, u32 scaler_version,
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u32 scaler_offset, const struct sde_format *format);
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u32 sde_hw_get_scaler3_ver(struct sde_hw_blk_reg_map *c,
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u32 scaler_offset);
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void sde_hw_csc_matrix_coeff_setup(struct sde_hw_blk_reg_map *c,
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u32 csc_reg_off, struct sde_csc_cfg *data,
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u32 shift_bit);
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void sde_hw_csc_setup(struct sde_hw_blk_reg_map *c,
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u32 csc_reg_off,
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struct sde_csc_cfg *data, bool csc10);
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uint32_t sde_copy_formats(
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struct sde_format_extended *dst_list,
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uint32_t dst_list_size,
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uint32_t dst_list_pos,
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const struct sde_format_extended *src_list,
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uint32_t src_list_size);
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uint32_t sde_get_linetime(struct drm_display_mode *mode);
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static inline bool is_qseed3_rev_qseed3lite(struct sde_mdss_cfg *sde_cfg)
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{
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return ((sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3LITE) ?
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true : false);
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}
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#endif /* _SDE_HW_UTIL_H */
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