510c72ad2d
There were a number of places that made evil PAGE_SIZE == 4k assumptions that ended up breaking when trying to play with 8k and 64k page sizes, this fixes those up. The most significant change is the way we load THREAD_SIZE, previously this was done via: mov #(THREAD_SIZE >> 8), reg shll8 reg to avoid a memory access and allow the immediate load. With a 64k PAGE_SIZE, we're out of range for the immediate load size without resorting to special instructions available in later ISAs (movi20s and so on). The "workaround" for this is to bump up the shift to 10 and insert a shll2, which gives a bit more flexibility while still being much cheaper than a memory access. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
694 lines
14 KiB
ArmAsm
694 lines
14 KiB
ArmAsm
/*
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* arch/sh/kernel/entry.S
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*
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* Copyright (C) 1999, 2000, 2002 Niibe Yutaka
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* Copyright (C) 2003 - 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/sys.h>
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/unistd.h>
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#include <asm/cpu/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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! NOTE:
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! GNU as (as of 2.9.1) changes bf/s into bt/s and bra, when the address
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! to be jumped is too far, but it causes illegal slot exception.
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/*
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* entry.S contains the system-call and fault low-level handling routines.
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* This also contains the timer-interrupt handler, as well as all interrupts
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* and faults that can result in a task-switch.
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*
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* NOTE: This code handles signal-recognition, which happens every time
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* after a timer-interrupt and after each system call.
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*
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* NOTE: This code uses a convention that instructions in the delay slot
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* of a transfer-control instruction are indented by an extra space, thus:
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*
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* jmp @k0 ! control-transfer instruction
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* ldc k1, ssr ! delay slot
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*
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* Stack layout in 'ret_from_syscall':
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* ptrace needs to have all regs on the stack.
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* if the order here is changed, it needs to be
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* updated in ptrace.c and ptrace.h
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*
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* r0
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* ...
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* r15 = stack pointer
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* spc
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* pr
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* ssr
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* gbr
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* mach
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* macl
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* syscall #
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*
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*/
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#if defined(CONFIG_KGDB_NMI)
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NMI_VEC = 0x1c0 ! Must catch early for debounce
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#endif
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/* Offsets to the stack */
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OFF_R0 = 0 /* Return value. New ABI also arg4 */
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OFF_R1 = 4 /* New ABI: arg5 */
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OFF_R2 = 8 /* New ABI: arg6 */
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OFF_R3 = 12 /* New ABI: syscall_nr */
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OFF_R4 = 16 /* New ABI: arg0 */
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OFF_R5 = 20 /* New ABI: arg1 */
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OFF_R6 = 24 /* New ABI: arg2 */
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OFF_R7 = 28 /* New ABI: arg3 */
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OFF_SP = (15*4)
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OFF_PC = (16*4)
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OFF_SR = (16*4+8)
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OFF_TRA = (16*4+6*4)
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#define k0 r0
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#define k1 r1
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#define k2 r2
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#define k3 r3
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#define k4 r4
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#define g_imask r6 /* r6_bank1 */
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#define k_g_imask r6_bank /* r6_bank1 */
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#define current r7 /* r7_bank1 */
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#include <asm/entry-macros.S>
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/*
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* Kernel mode register usage:
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* k0 scratch
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* k1 scratch
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* k2 scratch (Exception code)
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* k3 scratch (Return address)
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* k4 scratch
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* k5 reserved
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* k6 Global Interrupt Mask (0--15 << 4)
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* k7 CURRENT_THREAD_INFO (pointer to current thread info)
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*/
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!
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! TLB Miss / Initial Page write exception handling
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! _and_
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! TLB hits, but the access violate the protection.
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! It can be valid access, such as stack grow and/or C-O-W.
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!
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!
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! Find the pmd/pte entry and loadtlb
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! If it's not found, cause address error (SEGV)
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!
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! Although this could be written in assembly language (and it'd be faster),
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! this first version depends *much* on C implementation.
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!
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#if defined(CONFIG_MMU)
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.align 2
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ENTRY(tlb_miss_load)
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bra call_dpf
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mov #0, r5
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.align 2
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ENTRY(tlb_miss_store)
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bra call_dpf
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mov #1, r5
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.align 2
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ENTRY(initial_page_write)
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bra call_dpf
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mov #1, r5
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.align 2
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ENTRY(tlb_protection_violation_load)
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bra call_dpf
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mov #0, r5
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.align 2
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ENTRY(tlb_protection_violation_store)
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bra call_dpf
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mov #1, r5
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call_dpf:
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mov.l 1f, r0
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mov.l @r0, r6 ! address
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mov.l 3f, r0
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sti
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jmp @r0
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mov r15, r4 ! regs
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.align 2
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1: .long MMU_TEA
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3: .long do_page_fault
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.align 2
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ENTRY(address_error_load)
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bra call_dae
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mov #0,r5 ! writeaccess = 0
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.align 2
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ENTRY(address_error_store)
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bra call_dae
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mov #1,r5 ! writeaccess = 1
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.align 2
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call_dae:
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mov.l 1f, r0
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mov.l @r0, r6 ! address
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mov.l 2f, r0
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jmp @r0
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mov r15, r4 ! regs
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.align 2
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1: .long MMU_TEA
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2: .long do_address_error
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#endif /* CONFIG_MMU */
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#if defined(CONFIG_SH_STANDARD_BIOS)
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/* Unwind the stack and jmp to the debug entry */
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debug_kernel_fw:
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mov.l @r15+, r0
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mov.l @r15+, r1
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mov.l @r15+, r2
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mov.l @r15+, r3
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mov.l @r15+, r4
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mov.l @r15+, r5
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mov.l @r15+, r6
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mov.l @r15+, r7
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stc sr, r8
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mov.l 1f, r9 ! BL =1, RB=1, IMASK=0x0F
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or r9, r8
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ldc r8, sr ! here, change the register bank
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mov.l @r15+, r8
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mov.l @r15+, r9
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mov.l @r15+, r10
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mov.l @r15+, r11
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mov.l @r15+, r12
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mov.l @r15+, r13
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mov.l @r15+, r14
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mov.l @r15+, k0
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ldc.l @r15+, spc
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lds.l @r15+, pr
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mov.l @r15+, k1
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ldc.l @r15+, gbr
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lds.l @r15+, mach
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lds.l @r15+, macl
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mov k0, r15
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!
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mov.l 2f, k0
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mov.l @k0, k0
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jmp @k0
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ldc k1, ssr
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.align 2
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1: .long 0x300000f0
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2: .long gdb_vbr_vector
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#endif /* CONFIG_SH_STANDARD_BIOS */
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restore_all:
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mov.l @r15+, r0
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mov.l @r15+, r1
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mov.l @r15+, r2
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mov.l @r15+, r3
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mov.l @r15+, r4
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mov.l @r15+, r5
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mov.l @r15+, r6
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mov.l @r15+, r7
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!
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stc sr, r8
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mov.l 7f, r9
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or r9, r8 ! BL =1, RB=1
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ldc r8, sr ! here, change the register bank
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!
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mov.l @r15+, r8
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mov.l @r15+, r9
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mov.l @r15+, r10
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mov.l @r15+, r11
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mov.l @r15+, r12
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mov.l @r15+, r13
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mov.l @r15+, r14
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mov.l @r15+, k4 ! original stack pointer
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ldc.l @r15+, spc
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lds.l @r15+, pr
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mov.l @r15+, k3 ! original SR
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ldc.l @r15+, gbr
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lds.l @r15+, mach
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lds.l @r15+, macl
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add #4, r15 ! Skip syscall number
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!
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#ifdef CONFIG_SH_DSP
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mov.l @r15+, k0 ! DSP mode marker
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mov.l 5f, k1
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cmp/eq k0, k1 ! Do we have a DSP stack frame?
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bf skip_restore
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stc sr, k0 ! Enable CPU DSP mode
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or k1, k0 ! (within kernel it may be disabled)
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ldc k0, sr
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mov r2, k0 ! Backup r2
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! Restore DSP registers from stack
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mov r15, r2
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movs.l @r2+, a1
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movs.l @r2+, a0g
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movs.l @r2+, a1g
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movs.l @r2+, m0
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movs.l @r2+, m1
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mov r2, r15
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lds.l @r15+, a0
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lds.l @r15+, x0
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lds.l @r15+, x1
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lds.l @r15+, y0
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lds.l @r15+, y1
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lds.l @r15+, dsr
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ldc.l @r15+, rs
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ldc.l @r15+, re
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ldc.l @r15+, mod
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mov k0, r2 ! Restore r2
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skip_restore:
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#endif
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!
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! Calculate new SR value
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mov k3, k2 ! original SR value
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mov #0xf0, k1
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extu.b k1, k1
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not k1, k1
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and k1, k2 ! Mask orignal SR value
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!
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mov k3, k0 ! Calculate IMASK-bits
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shlr2 k0
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and #0x3c, k0
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cmp/eq #0x3c, k0
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bt/s 6f
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shll2 k0
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mov g_imask, k0
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!
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6: or k0, k2 ! Set the IMASK-bits
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ldc k2, ssr
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!
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#if defined(CONFIG_KGDB_NMI)
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! Clear in_nmi
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mov.l 6f, k0
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mov #0, k1
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mov.b k1, @k0
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#endif
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mov.l @r15+, k2 ! restore EXPEVT
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mov k4, r15
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rte
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nop
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.align 2
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5: .long 0x00001000 ! DSP
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7: .long 0x30000000
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! common exception handler
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#include "../../entry-common.S"
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! Exception Vector Base
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!
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! Should be aligned page boundary.
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!
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.balign 4096,0,4096
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ENTRY(vbr_base)
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.long 0
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!
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.balign 256,0,256
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general_exception:
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mov.l 1f, k2
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mov.l 2f, k3
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bra handle_exception
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mov.l @k2, k2
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.align 2
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1: .long EXPEVT
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2: .long ret_from_exception
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!
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!
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/* This code makes some assumptions to improve performance.
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* Make sure they are stil true. */
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#if PTRS_PER_PGD != PTRS_PER_PTE
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#error PGD and PTE sizes don't match
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#endif
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/* gas doesn't flag impossible values for mov #immediate as an error */
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#if (_PAGE_PRESENT >> 2) > 0x7f
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#error cannot load PAGE_PRESENT as an immediate
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#endif
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#if _PAGE_DIRTY > 0x7f
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#error cannot load PAGE_DIRTY as an immediate
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#endif
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#if (_PAGE_PRESENT << 2) != _PAGE_ACCESSED
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#error cannot derive PAGE_ACCESSED from PAGE_PRESENT
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#endif
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#if defined(CONFIG_CPU_SH4)
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#define ldmmupteh(r) mov.l 8f, r
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#else
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#define ldmmupteh(r) mov #MMU_PTEH, r
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#endif
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.balign 1024,0,1024
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tlb_miss:
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#ifdef COUNT_EXCEPTIONS
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! Increment the counts
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mov.l 9f, k1
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mov.l @k1, k2
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add #1, k2
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mov.l k2, @k1
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#endif
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! k0 scratch
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! k1 pgd and pte pointers
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! k2 faulting address
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! k3 pgd and pte index masks
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! k4 shift
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! Load up the pgd entry (k1)
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ldmmupteh(k0) ! 9 LS (latency=2) MMU_PTEH
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mov.w 4f, k3 ! 8 LS (latency=2) (PTRS_PER_PGD-1) << 2
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mov #-(PGDIR_SHIFT-2), k4 ! 6 EX
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mov.l @(MMU_TEA-MMU_PTEH,k0), k2 ! 18 LS (latency=2)
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mov.l @(MMU_TTB-MMU_PTEH,k0), k1 ! 18 LS (latency=2)
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mov k2, k0 ! 5 MT (latency=0)
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shld k4, k0 ! 99 EX
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and k3, k0 ! 78 EX
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mov.l @(k0, k1), k1 ! 21 LS (latency=2)
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mov #-(PAGE_SHIFT-2), k4 ! 6 EX
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! Load up the pte entry (k2)
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mov k2, k0 ! 5 MT (latency=0)
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shld k4, k0 ! 99 EX
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tst k1, k1 ! 86 MT
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bt 20f ! 110 BR
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and k3, k0 ! 78 EX
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mov.w 5f, k4 ! 8 LS (latency=2) _PAGE_PRESENT
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mov.l @(k0, k1), k2 ! 21 LS (latency=2)
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add k0, k1 ! 49 EX
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#ifdef CONFIG_CPU_HAS_PTEA
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! Test the entry for present and _PAGE_ACCESSED
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mov #-28, k3 ! 6 EX
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mov k2, k0 ! 5 MT (latency=0)
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tst k4, k2 ! 68 MT
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shld k3, k0 ! 99 EX
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bt 20f ! 110 BR
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! Set PTEA register
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! MMU_PTEA = ((pteval >> 28) & 0xe) | (pteval & 0x1)
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!
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! k0=pte>>28, k1=pte*, k2=pte, k3=<unused>, k4=_PAGE_PRESENT
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and #0xe, k0 ! 79 EX
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mov k0, k3 ! 5 MT (latency=0)
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mov k2, k0 ! 5 MT (latency=0)
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and #1, k0 ! 79 EX
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or k0, k3 ! 82 EX
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ldmmupteh(k0) ! 9 LS (latency=2)
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shll2 k4 ! 101 EX _PAGE_ACCESSED
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tst k4, k2 ! 68 MT
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mov.l k3, @(MMU_PTEA-MMU_PTEH,k0) ! 27 LS
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mov.l 7f, k3 ! 9 LS (latency=2) _PAGE_FLAGS_HARDWARE_MASK
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! k0=MMU_PTEH, k1=pte*, k2=pte, k3=_PAGE_FLAGS_HARDWARE, k4=_PAGE_ACCESSED
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#else
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! Test the entry for present and _PAGE_ACCESSED
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mov.l 7f, k3 ! 9 LS (latency=2) _PAGE_FLAGS_HARDWARE_MASK
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tst k4, k2 ! 68 MT
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shll2 k4 ! 101 EX _PAGE_ACCESSED
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ldmmupteh(k0) ! 9 LS (latency=2)
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bt 20f ! 110 BR
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tst k4, k2 ! 68 MT
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! k0=MMU_PTEH, k1=pte*, k2=pte, k3=_PAGE_FLAGS_HARDWARE, k4=_PAGE_ACCESSED
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#endif
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! Set up the entry
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and k2, k3 ! 78 EX
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bt/s 10f ! 108 BR
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mov.l k3, @(MMU_PTEL-MMU_PTEH,k0) ! 27 LS
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ldtlb ! 128 CO
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! At least one instruction between ldtlb and rte
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nop ! 119 NOP
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rte ! 126 CO
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nop ! 119 NOP
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10: or k4, k2 ! 82 EX
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ldtlb ! 128 CO
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! At least one instruction between ldtlb and rte
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mov.l k2, @k1 ! 27 LS
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rte ! 126 CO
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! Note we cannot execute mov here, because it is executed after
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! restoring SSR, so would be executed in user space.
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nop ! 119 NOP
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.align 5
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! Once cache line if possible...
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1: .long swapper_pg_dir
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4: .short (PTRS_PER_PGD-1) << 2
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5: .short _PAGE_PRESENT
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7: .long _PAGE_FLAGS_HARDWARE_MASK
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8: .long MMU_PTEH
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#ifdef COUNT_EXCEPTIONS
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9: .long exception_count_miss
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#endif
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! Either pgd or pte not present
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20: mov.l 1f, k2
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mov.l 4f, k3
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bra handle_exception
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mov.l @k2, k2
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!
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.balign 512,0,512
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interrupt:
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mov.l 2f, k2
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mov.l 3f, k3
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#if defined(CONFIG_KGDB_NMI)
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! Debounce (filter nested NMI)
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mov.l @k2, k0
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mov.l 5f, k1
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cmp/eq k1, k0
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bf 0f
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mov.l 6f, k1
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tas.b @k1
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bt 0f
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rte
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nop
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.align 2
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5: .long NMI_VEC
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6: .long in_nmi
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0:
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|
#endif /* defined(CONFIG_KGDB_NMI) */
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bra handle_exception
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|
mov #-1, k2 ! interrupt exception marker
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|
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|
.align 2
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|
1: .long EXPEVT
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|
2: .long INTEVT
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|
3: .long ret_from_irq
|
|
4: .long ret_from_exception
|
|
|
|
!
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|
!
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|
.align 2
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|
ENTRY(handle_exception)
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|
! Using k0, k1 for scratch registers (r0_bank1, r1_bank),
|
|
! save all registers onto stack.
|
|
!
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|
stc ssr, k0 ! Is it from kernel space?
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shll k0 ! Check MD bit (bit30) by shifting it into...
|
|
shll k0 ! ...the T bit
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|
bt/s 1f ! It's a kernel to kernel transition.
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|
mov r15, k0 ! save original stack to k0
|
|
/* User space to kernel */
|
|
mov #(THREAD_SIZE >> 10), k1
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|
shll8 k1 ! k1 := THREAD_SIZE
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|
shll2 k1
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|
add current, k1
|
|
mov k1, r15 ! change to kernel stack
|
|
!
|
|
1: mov.l 2f, k1
|
|
!
|
|
#ifdef CONFIG_SH_DSP
|
|
mov.l r2, @-r15 ! Save r2, we need another reg
|
|
stc sr, k4
|
|
mov.l 1f, r2
|
|
tst r2, k4 ! Check if in DSP mode
|
|
mov.l @r15+, r2 ! Restore r2 now
|
|
bt/s skip_save
|
|
mov #0, k4 ! Set marker for no stack frame
|
|
|
|
mov r2, k4 ! Backup r2 (in k4) for later
|
|
|
|
! Save DSP registers on stack
|
|
stc.l mod, @-r15
|
|
stc.l re, @-r15
|
|
stc.l rs, @-r15
|
|
sts.l dsr, @-r15
|
|
sts.l y1, @-r15
|
|
sts.l y0, @-r15
|
|
sts.l x1, @-r15
|
|
sts.l x0, @-r15
|
|
sts.l a0, @-r15
|
|
|
|
! GAS is broken, does not generate correct "movs.l Ds,@-As" instr.
|
|
|
|
! FIXME: Make sure that this is still the case with newer toolchains,
|
|
! as we're not at all interested in supporting ancient toolchains at
|
|
! this point. -- PFM.
|
|
|
|
mov r15, r2
|
|
.word 0xf653 ! movs.l a1, @-r2
|
|
.word 0xf6f3 ! movs.l a0g, @-r2
|
|
.word 0xf6d3 ! movs.l a1g, @-r2
|
|
.word 0xf6c3 ! movs.l m0, @-r2
|
|
.word 0xf6e3 ! movs.l m1, @-r2
|
|
mov r2, r15
|
|
|
|
mov k4, r2 ! Restore r2
|
|
mov.l 1f, k4 ! Force DSP stack frame
|
|
skip_save:
|
|
mov.l k4, @-r15 ! Push DSP mode marker onto stack
|
|
#endif
|
|
! Save the user registers on the stack.
|
|
mov.l k2, @-r15 ! EXPEVT
|
|
|
|
mov #-1, k4
|
|
mov.l k4, @-r15 ! set TRA (default: -1)
|
|
!
|
|
sts.l macl, @-r15
|
|
sts.l mach, @-r15
|
|
stc.l gbr, @-r15
|
|
stc.l ssr, @-r15
|
|
sts.l pr, @-r15
|
|
stc.l spc, @-r15
|
|
!
|
|
lds k3, pr ! Set the return address to pr
|
|
!
|
|
mov.l k0, @-r15 ! save orignal stack
|
|
mov.l r14, @-r15
|
|
mov.l r13, @-r15
|
|
mov.l r12, @-r15
|
|
mov.l r11, @-r15
|
|
mov.l r10, @-r15
|
|
mov.l r9, @-r15
|
|
mov.l r8, @-r15
|
|
!
|
|
stc sr, r8 ! Back to normal register bank, and
|
|
or k1, r8 ! Block all interrupts
|
|
mov.l 3f, k1
|
|
and k1, r8 ! ...
|
|
ldc r8, sr ! ...changed here.
|
|
!
|
|
mov.l r7, @-r15
|
|
mov.l r6, @-r15
|
|
mov.l r5, @-r15
|
|
mov.l r4, @-r15
|
|
mov.l r3, @-r15
|
|
mov.l r2, @-r15
|
|
mov.l r1, @-r15
|
|
mov.l r0, @-r15
|
|
|
|
/*
|
|
* This gets a bit tricky.. in the INTEVT case we don't want to use
|
|
* the VBR offset as a destination in the jump call table, since all
|
|
* of the destinations are the same. In this case, (interrupt) sets
|
|
* a marker in r2 (now r2_bank since SR.RB changed), which we check
|
|
* to determine the exception type. For all other exceptions, we
|
|
* forcibly read EXPEVT from memory and fix up the jump address, in
|
|
* the interrupt exception case we jump to do_IRQ() and defer the
|
|
* INTEVT read until there. As a bonus, we can also clean up the SR.RB
|
|
* checks that do_IRQ() was doing..
|
|
*/
|
|
stc r2_bank, r8
|
|
cmp/pz r8
|
|
bf interrupt_exception
|
|
shlr2 r8
|
|
shlr r8
|
|
|
|
#ifdef COUNT_EXCEPTIONS
|
|
mov.l 5f, r9
|
|
add r8, r9
|
|
mov.l @r9, r10
|
|
add #1, r10
|
|
mov.l r10, @r9
|
|
#endif
|
|
|
|
mov.l 4f, r9
|
|
add r8, r9
|
|
mov.l @r9, r9
|
|
jmp @r9
|
|
nop
|
|
rts
|
|
nop
|
|
|
|
.align 2
|
|
1: .long 0x00001000 ! DSP=1
|
|
2: .long 0x000080f0 ! FD=1, IMASK=15
|
|
3: .long 0xcfffffff ! RB=0, BL=0
|
|
4: .long exception_handling_table
|
|
#ifdef COUNT_EXCEPTIONS
|
|
5: .long exception_count_table
|
|
#endif
|
|
|
|
interrupt_exception:
|
|
mov.l 1f, r9
|
|
jmp @r9
|
|
nop
|
|
rts
|
|
nop
|
|
|
|
.align 2
|
|
1: .long do_IRQ
|
|
|
|
.align 2
|
|
ENTRY(exception_none)
|
|
rts
|
|
nop
|