7b5dea1234
Wakeup sources on PXA3 are enabled at two levels. First, the MFP configuration has to be set to enable which edges a specific pin will trigger a wakeup. The pin also has to be routed to a functional unit. Lastly, the functional unit must be enabled as a wakeup source in the appropriate AD*ER registers (AD2D0ER for standby resume.) This doesn't fit well with the IRQ wake scheme - we currently do a best effort conversion from IRQ numbers to functional unit wake enable bits. For instance, there's several USB client related enable bits but there's no corresponding IRQs to determine which you'd want. Conversely, there's a single enable bit covering several functional units. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
473 lines
10 KiB
C
473 lines
10 KiB
C
/*
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* linux/arch/arm/mach-pxa/pxa3xx.c
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*
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* code specific to pxa3xx aka Monahans
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*
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* Copyright (C) 2006 Marvell International Ltd.
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*
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* 2007-09-02: eric miao <eric.miao@marvell.com>
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* initial version
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/hardware.h>
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#include <asm/arch/pxa3xx-regs.h>
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#include <asm/arch/ohci.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/ssp.h>
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#include "generic.h"
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#include "devices.h"
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#include "clock.h"
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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/* Ring Oscillator Clock: 60MHz */
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#define RO_CLK 60000000
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#define ACCR_D0CS (1 << 26)
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/* crystal frequency to static memory controller multiplier (SMCFS) */
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static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
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/* crystal frequency to HSIO bus frequency multiplier (HSS) */
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static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa3xx_get_clk_frequency_khz(int info)
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{
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unsigned long acsr, xclkcfg;
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unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
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/* Read XCLKCFG register turbo bit */
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__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
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t = xclkcfg & 0x1;
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acsr = ACSR;
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xl = acsr & 0x1f;
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xn = (acsr >> 8) & 0x7;
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hss = (acsr >> 14) & 0x3;
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XL = xl * BASE_CLK;
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XN = xn * XL;
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ro = acsr & ACCR_D0CS;
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CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
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HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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if (info) {
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pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
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RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
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(ro) ? "" : "in");
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pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
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XL / 1000000, (XL % 1000000) / 10000, xl);
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pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
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XN / 1000000, (XN % 1000000) / 10000, xn,
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(t) ? "" : "in");
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pr_info("HSIO bus clock: %d.%02dMHz\n",
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HSS / 1000000, (HSS % 1000000) / 10000);
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}
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return CLK;
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}
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/*
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* Return the current static memory controller clock frequency
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* in units of 10kHz
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*/
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unsigned int pxa3xx_get_memclk_frequency_10khz(void)
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{
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unsigned long acsr;
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unsigned int smcfs, clk = 0;
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acsr = ACSR;
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smcfs = (acsr >> 23) & 0x7;
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clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
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return (clk / 10000);
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}
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/*
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* Return the current HSIO bus clock frequency
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*/
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static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
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{
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unsigned long acsr;
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unsigned int hss, hsio_clk;
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acsr = ACSR;
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hss = (acsr >> 14) & 0x3;
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hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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return hsio_clk;
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}
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static void clk_pxa3xx_cken_enable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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local_irq_disable();
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if (clk->cken < 32)
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CKENA |= mask;
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else
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CKENB |= mask;
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local_irq_enable();
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}
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static void clk_pxa3xx_cken_disable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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local_irq_disable();
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if (clk->cken < 32)
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CKENA &= ~mask;
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else
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CKENB &= ~mask;
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local_irq_enable();
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}
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static const struct clkops clk_pxa3xx_cken_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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};
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static const struct clkops clk_pxa3xx_hsio_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_hsio_getrate,
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};
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#define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \
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{ \
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.name = _name, \
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.dev = _dev, \
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.ops = &clk_pxa3xx_cken_ops, \
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.rate = _rate, \
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.cken = CKEN_##_cken, \
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.delay = _delay, \
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}
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#define PXA3xx_CK(_name, _cken, _ops, _dev) \
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{ \
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.name = _name, \
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.dev = _dev, \
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.ops = _ops, \
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.cken = CKEN_##_cken, \
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}
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static struct clk pxa3xx_clks[] = {
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PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
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PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
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PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
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PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
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PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
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PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
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PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
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PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
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PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
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PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
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PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
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PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
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PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
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PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
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PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
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};
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#ifdef CONFIG_PM
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#define SLEEP_SAVE_SIZE 4
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#define ISRAM_START 0x5c000000
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#define ISRAM_SIZE SZ_256K
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static void __iomem *sram;
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static unsigned long wakeup_src;
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static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
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{
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pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB);
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if (CKENA & (1 << CKEN_USBH)) {
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printk(KERN_ERR "PM: USB host clock not stopped?\n");
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CKENA &= ~(1 << CKEN_USBH);
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}
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// CKENA |= 1 << (CKEN_ISC & 31);
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/*
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* Low power modes require the HSIO2 clock to be enabled.
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*/
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CKENB |= 1 << (CKEN_HSIO2 & 31);
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}
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static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
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{
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CKENB &= ~(1 << (CKEN_HSIO2 & 31));
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}
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/*
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* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
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* memory controller has to be reinitialised, so we place some code
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* in the SRAM to perform this function.
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*
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* We disable FIQs across the standby - otherwise, we might receive a
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* FIQ while the SDRAM is unavailable.
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*/
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static void pxa3xx_cpu_standby(unsigned int pwrmode)
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{
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extern const char pm_enter_standby_start[], pm_enter_standby_end[];
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void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
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memcpy_toio(sram + 0x8000, pm_enter_standby_start,
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pm_enter_standby_end - pm_enter_standby_start);
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AD2D0SR = ~0;
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AD2D1SR = ~0;
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AD2D0ER = wakeup_src;
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AD2D1ER = 0;
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ASCR = ASCR;
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ARSR = ARSR;
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local_fiq_disable();
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fn(pwrmode);
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local_fiq_enable();
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AD2D0ER = 0;
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AD2D1ER = 0;
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printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
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}
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static void pxa3xx_cpu_pm_enter(suspend_state_t state)
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{
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/*
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* Don't sleep if no wakeup sources are defined
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*/
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if (wakeup_src == 0)
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return;
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switch (state) {
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case PM_SUSPEND_STANDBY:
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pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
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break;
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case PM_SUSPEND_MEM:
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break;
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}
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}
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static int pxa3xx_cpu_pm_valid(suspend_state_t state)
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{
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return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
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}
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static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
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.save_size = SLEEP_SAVE_SIZE,
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.save = pxa3xx_cpu_pm_save,
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.restore = pxa3xx_cpu_pm_restore,
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.valid = pxa3xx_cpu_pm_valid,
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.enter = pxa3xx_cpu_pm_enter,
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};
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static void __init pxa3xx_init_pm(void)
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{
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sram = ioremap(ISRAM_START, ISRAM_SIZE);
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if (!sram) {
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printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
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return;
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}
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/*
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* Since we copy wakeup code into the SRAM, we need to ensure
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* that it is preserved over the low power modes. Note: bit 8
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* is undocumented in the developer manual, but must be set.
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*/
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AD1R |= ADXR_L2 | ADXR_R0;
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AD2R |= ADXR_L2 | ADXR_R0;
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AD3R |= ADXR_L2 | ADXR_R0;
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/*
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* Clear the resume enable registers.
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*/
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AD1D0ER = 0;
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AD2D0ER = 0;
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AD2D1ER = 0;
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AD3ER = 0;
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pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
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}
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static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
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{
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unsigned long flags, mask = 0;
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switch (irq) {
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case IRQ_SSP3:
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mask = ADXER_MFP_WSSP3;
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break;
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case IRQ_MSL:
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mask = ADXER_WMSL0;
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break;
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case IRQ_USBH2:
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case IRQ_USBH1:
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mask = ADXER_WUSBH;
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break;
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case IRQ_KEYPAD:
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mask = ADXER_WKP;
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break;
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case IRQ_AC97:
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mask = ADXER_MFP_WAC97;
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break;
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case IRQ_USIM:
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mask = ADXER_WUSIM0;
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break;
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case IRQ_SSP2:
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mask = ADXER_MFP_WSSP2;
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break;
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case IRQ_I2C:
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mask = ADXER_MFP_WI2C;
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break;
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case IRQ_STUART:
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mask = ADXER_MFP_WUART3;
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break;
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case IRQ_BTUART:
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mask = ADXER_MFP_WUART2;
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break;
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case IRQ_FFUART:
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mask = ADXER_MFP_WUART1;
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break;
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case IRQ_MMC:
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mask = ADXER_MFP_WMMC1;
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break;
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case IRQ_SSP:
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mask = ADXER_MFP_WSSP1;
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break;
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case IRQ_RTCAlrm:
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mask = ADXER_WRTC;
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break;
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case IRQ_SSP4:
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mask = ADXER_MFP_WSSP4;
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break;
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case IRQ_TSI:
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mask = ADXER_WTSI;
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break;
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case IRQ_USIM2:
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mask = ADXER_WUSIM1;
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break;
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case IRQ_MMC2:
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mask = ADXER_MFP_WMMC2;
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break;
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case IRQ_NAND:
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mask = ADXER_MFP_WFLASH;
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break;
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case IRQ_USB2:
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mask = ADXER_WUSB2;
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break;
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case IRQ_WAKEUP0:
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mask = ADXER_WEXTWAKE0;
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break;
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case IRQ_WAKEUP1:
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mask = ADXER_WEXTWAKE1;
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break;
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case IRQ_MMC3:
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mask = ADXER_MFP_GEN12;
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break;
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}
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local_irq_save(flags);
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if (on)
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wakeup_src |= mask;
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else
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wakeup_src &= ~mask;
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local_irq_restore(flags);
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return 0;
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}
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static void pxa3xx_init_irq_pm(void)
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{
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pxa_init_irq_set_wake(pxa3xx_set_wake);
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}
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#else
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static inline void pxa3xx_init_pm(void) {}
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static inline void pxa3xx_init_irq_pm(void) {}
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#endif
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void __init pxa3xx_init_irq(void)
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{
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/* enable CP6 access */
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u32 value;
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__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
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value |= (1 << 6);
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__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
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pxa_init_irq_low();
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pxa_init_irq_high();
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pxa_init_irq_gpio(128);
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pxa3xx_init_irq_pm();
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}
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/*
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* device registration specific to PXA3xx.
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*/
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static struct platform_device *devices[] __initdata = {
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&pxa_device_udc,
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&pxa_device_ffuart,
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&pxa_device_btuart,
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&pxa_device_stuart,
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&pxa_device_i2s,
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&pxa_device_rtc,
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&pxa27x_device_ssp1,
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&pxa27x_device_ssp2,
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&pxa27x_device_ssp3,
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&pxa3xx_device_ssp4,
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};
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static int __init pxa3xx_init(void)
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{
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int ret = 0;
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if (cpu_is_pxa3xx()) {
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clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
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if ((ret = pxa_init_dma(32)))
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return ret;
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pxa3xx_init_pm();
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return platform_add_devices(devices, ARRAY_SIZE(devices));
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}
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return 0;
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}
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subsys_initcall(pxa3xx_init);
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