5300db887e
x86_cpuinfo is one more to the family of "not fundamentally different" structs. It's unified in processor.h, with very specific fields enclosed around ifdefs. Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
297 lines
8.2 KiB
C
297 lines
8.2 KiB
C
/*
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* Copyright (C) 1994 Linus Torvalds
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*/
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#ifndef __ASM_I386_PROCESSOR_H
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#define __ASM_I386_PROCESSOR_H
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#include <asm/vm86.h>
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#include <asm/math_emu.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/sigcontext.h>
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#include <asm/cpufeature.h>
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#include <asm/msr.h>
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#include <asm/system.h>
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#include <linux/threads.h>
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#include <linux/init.h>
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#include <asm/desc_defs.h>
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/*
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* capabilities of CPUs
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*/
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extern struct cpuinfo_x86 new_cpu_data;
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extern struct tss_struct doublefault_tss;
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/*
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* the following now lives in the per cpu area:
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* extern int cpu_llc_id[NR_CPUS];
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*/
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DECLARE_PER_CPU(u8, cpu_llc_id);
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extern char ignore_fpu_irq;
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void __init cpu_detect(struct cpuinfo_x86 *c);
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extern void identify_boot_cpu(void);
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extern void identify_secondary_cpu(struct cpuinfo_x86 *);
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#ifdef CONFIG_X86_HT
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extern void detect_ht(struct cpuinfo_x86 *c);
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#else
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static inline void detect_ht(struct cpuinfo_x86 *c) {}
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#endif
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/* from system description table in BIOS. Mostly for MCA use, but
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others may find it useful. */
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extern unsigned int machine_id;
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extern unsigned int machine_submodel_id;
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extern unsigned int BIOS_revision;
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extern unsigned int mca_pentium_flag;
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/*
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* User space process size: 3GB (default).
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*/
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#define TASK_SIZE (PAGE_OFFSET)
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struct i387_fsave_struct {
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long cwd;
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long swd;
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long twd;
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long fip;
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long fcs;
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long foo;
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long fos;
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long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
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long status; /* software status information */
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};
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struct i387_fxsave_struct {
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unsigned short cwd;
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unsigned short swd;
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unsigned short twd;
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unsigned short fop;
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long fip;
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long fcs;
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long foo;
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long fos;
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long mxcsr;
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long mxcsr_mask;
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long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
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long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
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long padding[56];
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} __attribute__ ((aligned (16)));
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struct i387_soft_struct {
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long cwd;
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long swd;
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long twd;
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long fip;
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long fcs;
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long foo;
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long fos;
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long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
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unsigned char ftop, changed, lookahead, no_update, rm, alimit;
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struct info *info;
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unsigned long entry_eip;
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};
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union i387_union {
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struct i387_fsave_struct fsave;
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struct i387_fxsave_struct fxsave;
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struct i387_soft_struct soft;
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};
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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#define INIT_THREAD { \
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.sp0 = sizeof(init_stack) + (long)&init_stack, \
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.vm86_info = NULL, \
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.sysenter_cs = __KERNEL_CS, \
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.io_bitmap_ptr = NULL, \
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.fs = __KERNEL_PERCPU, \
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}
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/*
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* Note that the .io_bitmap member must be extra-big. This is because
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* the CPU will access an additional byte beyond the end of the IO
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* permission bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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#define INIT_TSS { \
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.x86_tss = { \
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.sp0 = sizeof(init_stack) + (long)&init_stack, \
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.ss0 = __KERNEL_DS, \
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.ss1 = __KERNEL_CS, \
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.io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
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}, \
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.io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
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}
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#define start_thread(regs, new_eip, new_esp) do { \
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__asm__("movl %0,%%gs": :"r" (0)); \
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regs->fs = 0; \
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set_fs(USER_DS); \
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regs->ds = __USER_DS; \
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regs->es = __USER_DS; \
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regs->ss = __USER_DS; \
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regs->cs = __USER_CS; \
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regs->ip = new_eip; \
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regs->sp = new_esp; \
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} while (0)
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extern unsigned long thread_saved_pc(struct task_struct *tsk);
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#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
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#define KSTK_TOP(info) \
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({ \
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unsigned long *__ptr = (unsigned long *)(info); \
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(unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
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})
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/*
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* The below -8 is to reserve 8 bytes on top of the ring0 stack.
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* This is necessary to guarantee that the entire "struct pt_regs"
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* is accessable even if the CPU haven't stored the SS/ESP registers
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* on the stack (interrupt gate does not save these registers
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* when switching to the same priv ring).
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* Therefore beware: accessing the ss/esp fields of the
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* "struct pt_regs" is possible, but they may contain the
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* completely wrong values.
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*/
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#define task_pt_regs(task) \
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({ \
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struct pt_regs *__regs__; \
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__regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
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__regs__ - 1; \
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})
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#define KSTK_ESP(task) (task_pt_regs(task)->sp)
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/* generic versions from gas */
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#define GENERIC_NOP1 ".byte 0x90\n"
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#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
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#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
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#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
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#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
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#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
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#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
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#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
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/* Opteron nops */
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#define K8_NOP1 GENERIC_NOP1
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#define K8_NOP2 ".byte 0x66,0x90\n"
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#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
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#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
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#define K8_NOP5 K8_NOP3 K8_NOP2
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#define K8_NOP6 K8_NOP3 K8_NOP3
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#define K8_NOP7 K8_NOP4 K8_NOP3
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#define K8_NOP8 K8_NOP4 K8_NOP4
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/* K7 nops */
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/* uses eax dependencies (arbitary choice) */
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#define K7_NOP1 GENERIC_NOP1
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#define K7_NOP2 ".byte 0x8b,0xc0\n"
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#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
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#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
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#define K7_NOP5 K7_NOP4 ASM_NOP1
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#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
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#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
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#define K7_NOP8 K7_NOP7 ASM_NOP1
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/* P6 nops */
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/* uses eax dependencies (Intel-recommended choice) */
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#define P6_NOP1 GENERIC_NOP1
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#define P6_NOP2 ".byte 0x66,0x90\n"
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#define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
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#define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
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#define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
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#define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
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#define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
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#define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
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#ifdef CONFIG_MK8
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#define ASM_NOP1 K8_NOP1
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#define ASM_NOP2 K8_NOP2
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#define ASM_NOP3 K8_NOP3
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#define ASM_NOP4 K8_NOP4
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#define ASM_NOP5 K8_NOP5
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#define ASM_NOP6 K8_NOP6
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#define ASM_NOP7 K8_NOP7
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#define ASM_NOP8 K8_NOP8
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#elif defined(CONFIG_MK7)
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#define ASM_NOP1 K7_NOP1
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#define ASM_NOP2 K7_NOP2
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#define ASM_NOP3 K7_NOP3
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#define ASM_NOP4 K7_NOP4
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#define ASM_NOP5 K7_NOP5
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#define ASM_NOP6 K7_NOP6
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#define ASM_NOP7 K7_NOP7
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#define ASM_NOP8 K7_NOP8
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#elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \
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defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \
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defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4)
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#define ASM_NOP1 P6_NOP1
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#define ASM_NOP2 P6_NOP2
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#define ASM_NOP3 P6_NOP3
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#define ASM_NOP4 P6_NOP4
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#define ASM_NOP5 P6_NOP5
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#define ASM_NOP6 P6_NOP6
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#define ASM_NOP7 P6_NOP7
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#define ASM_NOP8 P6_NOP8
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#else
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#define ASM_NOP1 GENERIC_NOP1
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#define ASM_NOP2 GENERIC_NOP2
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#define ASM_NOP3 GENERIC_NOP3
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#define ASM_NOP4 GENERIC_NOP4
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#define ASM_NOP5 GENERIC_NOP5
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#define ASM_NOP6 GENERIC_NOP6
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#define ASM_NOP7 GENERIC_NOP7
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#define ASM_NOP8 GENERIC_NOP8
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#endif
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#define ASM_NOP_MAX 8
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/* Prefetch instructions for Pentium III and AMD Athlon */
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/* It's not worth to care about 3dnow! prefetches for the K6
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because they are microcoded there and very slow.
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However we don't do prefetches for pre XP Athlons currently
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That should be fixed. */
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static inline void prefetch(const void *x)
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{
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alternative_input(ASM_NOP4,
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"prefetchnta (%1)",
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X86_FEATURE_XMM,
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"r" (x));
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}
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#define ARCH_HAS_PREFETCH
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/* 3dnow! prefetch to get an exclusive cache line. Useful for
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spinlocks to avoid one state transition in the cache coherency protocol. */
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static inline void prefetchw(const void *x)
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{
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alternative_input(ASM_NOP4,
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"prefetchw (%1)",
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X86_FEATURE_3DNOW,
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"r" (x));
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}
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extern void enable_sep_cpu(void);
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extern int sysenter_setup(void);
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/* Defined in head.S */
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extern struct desc_ptr early_gdt_descr;
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extern void cpu_set_gdt(int);
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extern void switch_to_new_gdt(void);
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extern void cpu_init(void);
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extern void init_gdt(int cpu);
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#endif /* __ASM_I386_PROCESSOR_H */
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