97dcb82de6
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
118 lines
2.8 KiB
C
118 lines
2.8 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
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* Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2004 Maciej W. Rozycki
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Routines for generic manipulation of the interrupts found on the MIPS
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* Sead board.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/mips-boards/seadint.h>
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static inline int clz(unsigned long x)
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{
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__asm__ (
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" .set push \n"
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" .set mips32 \n"
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" clz %0, %1 \n"
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" .set pop \n"
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: "=r" (x)
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: "r" (x));
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return x;
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}
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/*
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* Version of ffs that only looks at bits 12..15.
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*/
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static inline unsigned int irq_ffs(unsigned int pending)
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{
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#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
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return -clz(pending) + 31 - CAUSEB_IP;
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#else
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unsigned int a0 = 7;
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unsigned int t0;
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t0 = s0 & 0xf000;
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t0 = t0 < 1;
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t0 = t0 << 2;
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a0 = a0 - t0;
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s0 = s0 << t0;
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t0 = s0 & 0xc000;
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t0 = t0 < 1;
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t0 = t0 << 1;
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a0 = a0 - t0;
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s0 = s0 << t0;
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t0 = s0 & 0x8000;
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t0 = t0 < 1;
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//t0 = t0 << 2;
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a0 = a0 - t0;
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//s0 = s0 << t0;
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return a0;
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#endif
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}
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/*
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* IRQs on the SEAD board look basically are combined together on hardware
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* interrupt 0 (MIPS IRQ 2)) like:
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*
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* MIPS IRQ Source
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 UART0 (hw0)
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* 3 UART1 (hw1)
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* 4 Hardware (ignored)
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* 5 Hardware (ignored)
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* 6 Hardware (ignored)
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* 7 R4k timer (what we use)
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*
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* We handle the IRQ according to _our_ priority which is:
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*
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* Highest ---- R4k Timer
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* Lowest ---- Combined hardware interrupt
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*
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* then we just return, if multiple IRQs are pending then we will just take
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* another exception, big deal.
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*/
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
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int irq;
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irq = irq_ffs(pending);
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if (irq >= 0)
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do_IRQ(MIPSCPU_INT_BASE + irq);
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else
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spurious_interrupt();
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}
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init();
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}
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