604 lines
17 KiB
C
604 lines
17 KiB
C
#ifndef __ALPHA_SYSTEM_H
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#define __ALPHA_SYSTEM_H
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#include <asm/pal.h>
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#include <asm/page.h>
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#include <asm/barrier.h>
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/*
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* System defines.. Note that this is included both from .c and .S
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* files, so it does only defines, not any C code.
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*/
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/*
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* We leave one page for the initial stack page, and one page for
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* the initial process structure. Also, the console eats 3 MB for
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* the initial bootloader (one of which we can reclaim later).
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*/
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#define BOOT_PCB 0x20000000
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#define BOOT_ADDR 0x20000000
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/* Remove when official MILO sources have ELF support: */
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#define BOOT_SIZE (16*1024)
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#ifdef CONFIG_ALPHA_LEGACY_START_ADDRESS
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#define KERNEL_START_PHYS 0x300000 /* Old bootloaders hardcoded this. */
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#else
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#define KERNEL_START_PHYS 0x1000000 /* required: Wildfire/Titan/Marvel */
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#endif
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#define KERNEL_START (PAGE_OFFSET+KERNEL_START_PHYS)
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#define SWAPPER_PGD KERNEL_START
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#define INIT_STACK (PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
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#define EMPTY_PGT (PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
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#define EMPTY_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
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#define ZERO_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)
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#define START_ADDR (PAGE_OFFSET+KERNEL_START_PHYS+0x10000)
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/*
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* This is setup by the secondary bootstrap loader. Because
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* the zero page is zeroed out as soon as the vm system is
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* initialized, we need to copy things out into a more permanent
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* place.
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*/
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#define PARAM ZERO_PGE
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#define COMMAND_LINE ((char*)(PARAM + 0x0000))
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#define INITRD_START (*(unsigned long *) (PARAM+0x100))
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#define INITRD_SIZE (*(unsigned long *) (PARAM+0x108))
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#ifndef __ASSEMBLY__
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#include <linux/kernel.h>
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/*
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* This is the logout header that should be common to all platforms
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* (assuming they are running OSF/1 PALcode, I guess).
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*/
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struct el_common {
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unsigned int size; /* size in bytes of logout area */
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unsigned int sbz1 : 30; /* should be zero */
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unsigned int err2 : 1; /* second error */
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unsigned int retry : 1; /* retry flag */
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unsigned int proc_offset; /* processor-specific offset */
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unsigned int sys_offset; /* system-specific offset */
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unsigned int code; /* machine check code */
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unsigned int frame_rev; /* frame revision */
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};
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/* Machine Check Frame for uncorrectable errors (Large format)
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* --- This is used to log uncorrectable errors such as
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* double bit ECC errors.
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* --- These errors are detected by both processor and systems.
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*/
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struct el_common_EV5_uncorrectable_mcheck {
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unsigned long shadow[8]; /* Shadow reg. 8-14, 25 */
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unsigned long paltemp[24]; /* PAL TEMP REGS. */
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unsigned long exc_addr; /* Address of excepting instruction*/
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unsigned long exc_sum; /* Summary of arithmetic traps. */
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unsigned long exc_mask; /* Exception mask (from exc_sum). */
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unsigned long pal_base; /* Base address for PALcode. */
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unsigned long isr; /* Interrupt Status Reg. */
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unsigned long icsr; /* CURRENT SETUP OF EV5 IBOX */
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unsigned long ic_perr_stat; /* I-CACHE Reg. <11> set Data parity
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<12> set TAG parity*/
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unsigned long dc_perr_stat; /* D-CACHE error Reg. Bits set to 1:
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<2> Data error in bank 0
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<3> Data error in bank 1
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<4> Tag error in bank 0
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<5> Tag error in bank 1 */
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unsigned long va; /* Effective VA of fault or miss. */
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unsigned long mm_stat; /* Holds the reason for D-stream
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fault or D-cache parity errors */
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unsigned long sc_addr; /* Address that was being accessed
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when EV5 detected Secondary cache
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failure. */
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unsigned long sc_stat; /* Helps determine if the error was
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TAG/Data parity(Secondary Cache)*/
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unsigned long bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */
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unsigned long ei_addr; /* Physical address of any transfer
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that is logged in EV5 EI_STAT */
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unsigned long fill_syndrome; /* For correcting ECC errors. */
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unsigned long ei_stat; /* Helps identify reason of any
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processor uncorrectable error
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at its external interface. */
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unsigned long ld_lock; /* Contents of EV5 LD_LOCK register*/
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};
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struct el_common_EV6_mcheck {
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unsigned int FrameSize; /* Bytes, including this field */
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unsigned int FrameFlags; /* <31> = Retry, <30> = Second Error */
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unsigned int CpuOffset; /* Offset to CPU-specific info */
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unsigned int SystemOffset; /* Offset to system-specific info */
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unsigned int MCHK_Code;
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unsigned int MCHK_Frame_Rev;
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unsigned long I_STAT; /* EV6 Internal Processor Registers */
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unsigned long DC_STAT; /* (See the 21264 Spec) */
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unsigned long C_ADDR;
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unsigned long DC1_SYNDROME;
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unsigned long DC0_SYNDROME;
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unsigned long C_STAT;
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unsigned long C_STS;
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unsigned long MM_STAT;
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unsigned long EXC_ADDR;
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unsigned long IER_CM;
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unsigned long ISUM;
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unsigned long RESERVED0;
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unsigned long PAL_BASE;
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unsigned long I_CTL;
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unsigned long PCTX;
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};
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extern void halt(void) __attribute__((noreturn));
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#define __halt() __asm__ __volatile__ ("call_pal %0 #halt" : : "i" (PAL_halt))
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#define switch_to(P,N,L) \
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do { \
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(L) = alpha_switch_to(virt_to_phys(&task_thread_info(N)->pcb), (P)); \
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check_mmu_context(); \
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} while (0)
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struct task_struct;
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extern struct task_struct *alpha_switch_to(unsigned long, struct task_struct*);
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible.
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*
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* TODO: fill this in!
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*/
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static inline void sched_cacheflush(void)
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{
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}
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#define imb() \
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__asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory")
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#define draina() \
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__asm__ __volatile__ ("call_pal %0 #draina" : : "i" (PAL_draina) : "memory")
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enum implver_enum {
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IMPLVER_EV4,
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IMPLVER_EV5,
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IMPLVER_EV6
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};
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#ifdef CONFIG_ALPHA_GENERIC
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#define implver() \
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({ unsigned long __implver; \
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__asm__ ("implver %0" : "=r"(__implver)); \
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(enum implver_enum) __implver; })
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#else
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/* Try to eliminate some dead code. */
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#ifdef CONFIG_ALPHA_EV4
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#define implver() IMPLVER_EV4
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#endif
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#ifdef CONFIG_ALPHA_EV5
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#define implver() IMPLVER_EV5
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#endif
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#if defined(CONFIG_ALPHA_EV6)
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#define implver() IMPLVER_EV6
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#endif
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#endif
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enum amask_enum {
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AMASK_BWX = (1UL << 0),
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AMASK_FIX = (1UL << 1),
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AMASK_CIX = (1UL << 2),
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AMASK_MAX = (1UL << 8),
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AMASK_PRECISE_TRAP = (1UL << 9),
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};
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#define amask(mask) \
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({ unsigned long __amask, __input = (mask); \
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__asm__ ("amask %1,%0" : "=r"(__amask) : "rI"(__input)); \
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__amask; })
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#define __CALL_PAL_R0(NAME, TYPE) \
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static inline TYPE NAME(void) \
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{ \
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register TYPE __r0 __asm__("$0"); \
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__asm__ __volatile__( \
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"call_pal %1 # " #NAME \
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:"=r" (__r0) \
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:"i" (PAL_ ## NAME) \
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:"$1", "$16", "$22", "$23", "$24", "$25"); \
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return __r0; \
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}
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#define __CALL_PAL_W1(NAME, TYPE0) \
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static inline void NAME(TYPE0 arg0) \
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{ \
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register TYPE0 __r16 __asm__("$16") = arg0; \
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__asm__ __volatile__( \
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"call_pal %1 # "#NAME \
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: "=r"(__r16) \
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: "i"(PAL_ ## NAME), "0"(__r16) \
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: "$1", "$22", "$23", "$24", "$25"); \
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}
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#define __CALL_PAL_W2(NAME, TYPE0, TYPE1) \
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static inline void NAME(TYPE0 arg0, TYPE1 arg1) \
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{ \
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register TYPE0 __r16 __asm__("$16") = arg0; \
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register TYPE1 __r17 __asm__("$17") = arg1; \
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__asm__ __volatile__( \
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"call_pal %2 # "#NAME \
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: "=r"(__r16), "=r"(__r17) \
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: "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \
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: "$1", "$22", "$23", "$24", "$25"); \
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}
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#define __CALL_PAL_RW1(NAME, RTYPE, TYPE0) \
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static inline RTYPE NAME(TYPE0 arg0) \
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{ \
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register RTYPE __r0 __asm__("$0"); \
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register TYPE0 __r16 __asm__("$16") = arg0; \
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__asm__ __volatile__( \
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"call_pal %2 # "#NAME \
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: "=r"(__r16), "=r"(__r0) \
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: "i"(PAL_ ## NAME), "0"(__r16) \
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: "$1", "$22", "$23", "$24", "$25"); \
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return __r0; \
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}
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#define __CALL_PAL_RW2(NAME, RTYPE, TYPE0, TYPE1) \
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static inline RTYPE NAME(TYPE0 arg0, TYPE1 arg1) \
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{ \
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register RTYPE __r0 __asm__("$0"); \
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register TYPE0 __r16 __asm__("$16") = arg0; \
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register TYPE1 __r17 __asm__("$17") = arg1; \
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__asm__ __volatile__( \
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"call_pal %3 # "#NAME \
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: "=r"(__r16), "=r"(__r17), "=r"(__r0) \
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: "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \
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: "$1", "$22", "$23", "$24", "$25"); \
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return __r0; \
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}
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__CALL_PAL_W1(cflush, unsigned long);
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__CALL_PAL_R0(rdmces, unsigned long);
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__CALL_PAL_R0(rdps, unsigned long);
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__CALL_PAL_R0(rdusp, unsigned long);
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__CALL_PAL_RW1(swpipl, unsigned long, unsigned long);
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__CALL_PAL_R0(whami, unsigned long);
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__CALL_PAL_W2(wrent, void*, unsigned long);
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__CALL_PAL_W1(wripir, unsigned long);
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__CALL_PAL_W1(wrkgp, unsigned long);
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__CALL_PAL_W1(wrmces, unsigned long);
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__CALL_PAL_RW2(wrperfmon, unsigned long, unsigned long, unsigned long);
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__CALL_PAL_W1(wrusp, unsigned long);
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__CALL_PAL_W1(wrvptptr, unsigned long);
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#define IPL_MIN 0
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#define IPL_SW0 1
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#define IPL_SW1 2
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#define IPL_DEV0 3
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#define IPL_DEV1 4
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#define IPL_TIMER 5
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#define IPL_PERF 6
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#define IPL_POWERFAIL 6
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#define IPL_MCHECK 7
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#define IPL_MAX 7
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#ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK
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#undef IPL_MIN
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#define IPL_MIN __min_ipl
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extern int __min_ipl;
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#endif
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#define getipl() (rdps() & 7)
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#define setipl(ipl) ((void) swpipl(ipl))
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#define local_irq_disable() do { setipl(IPL_MAX); barrier(); } while(0)
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#define local_irq_enable() do { barrier(); setipl(IPL_MIN); } while(0)
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#define local_save_flags(flags) ((flags) = rdps())
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#define local_irq_save(flags) do { (flags) = swpipl(IPL_MAX); barrier(); } while(0)
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#define local_irq_restore(flags) do { barrier(); setipl(flags); barrier(); } while(0)
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#define irqs_disabled() (getipl() == IPL_MAX)
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/*
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* TB routines..
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*/
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#define __tbi(nr,arg,arg1...) \
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({ \
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register unsigned long __r16 __asm__("$16") = (nr); \
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register unsigned long __r17 __asm__("$17"); arg; \
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__asm__ __volatile__( \
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"call_pal %3 #__tbi" \
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:"=r" (__r16),"=r" (__r17) \
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:"0" (__r16),"i" (PAL_tbi) ,##arg1 \
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:"$0", "$1", "$22", "$23", "$24", "$25"); \
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})
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#define tbi(x,y) __tbi(x,__r17=(y),"1" (__r17))
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#define tbisi(x) __tbi(1,__r17=(x),"1" (__r17))
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#define tbisd(x) __tbi(2,__r17=(x),"1" (__r17))
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#define tbis(x) __tbi(3,__r17=(x),"1" (__r17))
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#define tbiap() __tbi(-1, /* no second argument */)
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#define tbia() __tbi(-2, /* no second argument */)
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/*
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* Atomic exchange.
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* Since it can be used to implement critical sections
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* it must clobber "memory" (also for interrupts in UP).
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*/
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static inline unsigned long
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__xchg_u8(volatile char *m, unsigned long val)
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{
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unsigned long ret, tmp, addr64;
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__asm__ __volatile__(
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" andnot %4,7,%3\n"
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" insbl %1,%4,%1\n"
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"1: ldq_l %2,0(%3)\n"
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" extbl %2,%4,%0\n"
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" mskbl %2,%4,%2\n"
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" or %1,%2,%2\n"
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" stq_c %2,0(%3)\n"
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" beq %2,2f\n"
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#ifdef CONFIG_SMP
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" mb\n"
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#endif
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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: "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
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: "r" ((long)m), "1" (val) : "memory");
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return ret;
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}
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static inline unsigned long
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__xchg_u16(volatile short *m, unsigned long val)
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{
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unsigned long ret, tmp, addr64;
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__asm__ __volatile__(
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" andnot %4,7,%3\n"
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" inswl %1,%4,%1\n"
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"1: ldq_l %2,0(%3)\n"
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" extwl %2,%4,%0\n"
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" mskwl %2,%4,%2\n"
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" or %1,%2,%2\n"
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" stq_c %2,0(%3)\n"
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" beq %2,2f\n"
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#ifdef CONFIG_SMP
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" mb\n"
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#endif
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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: "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
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: "r" ((long)m), "1" (val) : "memory");
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return ret;
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}
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static inline unsigned long
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__xchg_u32(volatile int *m, unsigned long val)
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{
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unsigned long dummy;
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__asm__ __volatile__(
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"1: ldl_l %0,%4\n"
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" bis $31,%3,%1\n"
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" stl_c %1,%2\n"
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" beq %1,2f\n"
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#ifdef CONFIG_SMP
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" mb\n"
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#endif
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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: "=&r" (val), "=&r" (dummy), "=m" (*m)
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: "rI" (val), "m" (*m) : "memory");
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return val;
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}
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static inline unsigned long
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__xchg_u64(volatile long *m, unsigned long val)
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{
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unsigned long dummy;
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__asm__ __volatile__(
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"1: ldq_l %0,%4\n"
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" bis $31,%3,%1\n"
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" stq_c %1,%2\n"
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" beq %1,2f\n"
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#ifdef CONFIG_SMP
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" mb\n"
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#endif
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".subsection 2\n"
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"2: br 1b\n"
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".previous"
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: "=&r" (val), "=&r" (dummy), "=m" (*m)
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: "rI" (val), "m" (*m) : "memory");
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return val;
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}
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid xchg(). */
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extern void __xchg_called_with_bad_pointer(void);
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#define __xchg(ptr, x, size) \
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({ \
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unsigned long __xchg__res; \
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volatile void *__xchg__ptr = (ptr); \
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switch (size) { \
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case 1: __xchg__res = __xchg_u8(__xchg__ptr, x); break; \
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case 2: __xchg__res = __xchg_u16(__xchg__ptr, x); break; \
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case 4: __xchg__res = __xchg_u32(__xchg__ptr, x); break; \
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case 8: __xchg__res = __xchg_u64(__xchg__ptr, x); break; \
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default: __xchg_called_with_bad_pointer(); __xchg__res = x; \
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} \
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__xchg__res; \
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})
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#define xchg(ptr,x) \
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({ \
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__typeof__(*(ptr)) _x_ = (x); \
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(__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
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})
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#define tas(ptr) (xchg((ptr),1))
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/*
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* Atomic compare and exchange. Compare OLD with MEM, if identical,
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* store NEW in MEM. Return the initial value in MEM. Success is
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* indicated by comparing RETURN with OLD.
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*
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* The memory barrier should be placed in SMP only when we actually
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* make the change. If we don't change anything (so if the returned
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* prev is equal to old) then we aren't acquiring anything new and
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* we don't need any memory barrier as far I can tell.
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*/
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#define __HAVE_ARCH_CMPXCHG 1
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static inline unsigned long
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__cmpxchg_u8(volatile char *m, long old, long new)
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{
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unsigned long prev, tmp, cmp, addr64;
|
|
|
|
__asm__ __volatile__(
|
|
" andnot %5,7,%4\n"
|
|
" insbl %1,%5,%1\n"
|
|
"1: ldq_l %2,0(%4)\n"
|
|
" extbl %2,%5,%0\n"
|
|
" cmpeq %0,%6,%3\n"
|
|
" beq %3,2f\n"
|
|
" mskbl %2,%5,%2\n"
|
|
" or %1,%2,%2\n"
|
|
" stq_c %2,0(%4)\n"
|
|
" beq %2,3f\n"
|
|
#ifdef CONFIG_SMP
|
|
" mb\n"
|
|
#endif
|
|
"2:\n"
|
|
".subsection 2\n"
|
|
"3: br 1b\n"
|
|
".previous"
|
|
: "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
|
|
: "r" ((long)m), "Ir" (old), "1" (new) : "memory");
|
|
|
|
return prev;
|
|
}
|
|
|
|
static inline unsigned long
|
|
__cmpxchg_u16(volatile short *m, long old, long new)
|
|
{
|
|
unsigned long prev, tmp, cmp, addr64;
|
|
|
|
__asm__ __volatile__(
|
|
" andnot %5,7,%4\n"
|
|
" inswl %1,%5,%1\n"
|
|
"1: ldq_l %2,0(%4)\n"
|
|
" extwl %2,%5,%0\n"
|
|
" cmpeq %0,%6,%3\n"
|
|
" beq %3,2f\n"
|
|
" mskwl %2,%5,%2\n"
|
|
" or %1,%2,%2\n"
|
|
" stq_c %2,0(%4)\n"
|
|
" beq %2,3f\n"
|
|
#ifdef CONFIG_SMP
|
|
" mb\n"
|
|
#endif
|
|
"2:\n"
|
|
".subsection 2\n"
|
|
"3: br 1b\n"
|
|
".previous"
|
|
: "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
|
|
: "r" ((long)m), "Ir" (old), "1" (new) : "memory");
|
|
|
|
return prev;
|
|
}
|
|
|
|
static inline unsigned long
|
|
__cmpxchg_u32(volatile int *m, int old, int new)
|
|
{
|
|
unsigned long prev, cmp;
|
|
|
|
__asm__ __volatile__(
|
|
"1: ldl_l %0,%5\n"
|
|
" cmpeq %0,%3,%1\n"
|
|
" beq %1,2f\n"
|
|
" mov %4,%1\n"
|
|
" stl_c %1,%2\n"
|
|
" beq %1,3f\n"
|
|
#ifdef CONFIG_SMP
|
|
" mb\n"
|
|
#endif
|
|
"2:\n"
|
|
".subsection 2\n"
|
|
"3: br 1b\n"
|
|
".previous"
|
|
: "=&r"(prev), "=&r"(cmp), "=m"(*m)
|
|
: "r"((long) old), "r"(new), "m"(*m) : "memory");
|
|
|
|
return prev;
|
|
}
|
|
|
|
static inline unsigned long
|
|
__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
|
|
{
|
|
unsigned long prev, cmp;
|
|
|
|
__asm__ __volatile__(
|
|
"1: ldq_l %0,%5\n"
|
|
" cmpeq %0,%3,%1\n"
|
|
" beq %1,2f\n"
|
|
" mov %4,%1\n"
|
|
" stq_c %1,%2\n"
|
|
" beq %1,3f\n"
|
|
#ifdef CONFIG_SMP
|
|
" mb\n"
|
|
#endif
|
|
"2:\n"
|
|
".subsection 2\n"
|
|
"3: br 1b\n"
|
|
".previous"
|
|
: "=&r"(prev), "=&r"(cmp), "=m"(*m)
|
|
: "r"((long) old), "r"(new), "m"(*m) : "memory");
|
|
|
|
return prev;
|
|
}
|
|
|
|
/* This function doesn't exist, so you'll get a linker error
|
|
if something tries to do an invalid cmpxchg(). */
|
|
extern void __cmpxchg_called_with_bad_pointer(void);
|
|
|
|
static __always_inline unsigned long
|
|
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
|
|
{
|
|
switch (size) {
|
|
case 1:
|
|
return __cmpxchg_u8(ptr, old, new);
|
|
case 2:
|
|
return __cmpxchg_u16(ptr, old, new);
|
|
case 4:
|
|
return __cmpxchg_u32(ptr, old, new);
|
|
case 8:
|
|
return __cmpxchg_u64(ptr, old, new);
|
|
}
|
|
__cmpxchg_called_with_bad_pointer();
|
|
return old;
|
|
}
|
|
|
|
#define cmpxchg(ptr,o,n) \
|
|
({ \
|
|
__typeof__(*(ptr)) _o_ = (o); \
|
|
__typeof__(*(ptr)) _n_ = (n); \
|
|
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
|
|
(unsigned long)_n_, sizeof(*(ptr))); \
|
|
})
|
|
|
|
#endif /* __ASSEMBLY__ */
|
|
|
|
#define arch_align_stack(x) (x)
|
|
|
|
#endif
|