Abel Vesa e412625f38 clk: imx8mq: Fix usdhc parents order ... [ Upstream commit b159c63d82ff8ffddc6c6f0eb881b113b36ecad7 ] According to the latest RM (see Table 5-1. Clock Root Table), both usdhc root clocks have the parent order as follows: 000 - 25M_REF_CLK 001 - SYSTEM_PLL1_DIV2 010 - SYSTEM_PLL1_CLK 011 - SYSTEM_PLL2_DIV2 100 - SYSTEM_PLL3_CLK 101 - SYSTEM_PLL1_DIV3 110 - AUDIO_PLL2_CLK 111 - SYSTEM_PLL1_DIV8 So the audio_pll2_out and sys3_pll_out have to be swapped. Fixes: b80522040c ("clk: imx: Add clock driver for i.MX8MQ CCM") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reported-by: Cosmin Stefan Stoica <cosmin.stoica@nxp.com> Link: https://lore.kernel.org/r/1602753944-30757-1-git-send-email-abel.vesa@nxp.com Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2020-10-29 09:57:56 +01:00
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clk-busy.c
clk-composite-7ulp.c
clk-composite-8m.c
clk-cpu.c
clk-divider-gate.c
clk-fixup-div.c
clk-fixup-mux.c
clk-frac-pll.c
clk-gate2.c
clk-gate-exclusive.c
clk-imx1.c
clk-imx5.c
clk-imx6q.c
clk-imx6sl.c
clk-imx6sll.c
clk-imx6sx.c
clk-imx6ul.c
clk-imx7d.c
clk-imx7ulp.c
clk-imx8mm.c
clk-imx8mn.c
clk-imx8mq.c
clk-imx8qxp-lpcg.c
clk-imx8qxp-lpcg.h
clk-imx8qxp.c
clk-imx21.c
clk-imx25.c
clk-imx27.c
clk-imx31.c
clk-imx35.c
clk-lpcg-scu.c
clk-pfd.c
clk-pfdv2.c
clk-pll14xx.c
clk-pllv1.c
clk-pllv2.c
clk-pllv3.c
clk-pllv4.c
clk-sccg-pll.c
clk-scu.c
clk-scu.h
clk-vf610.c
clk.c
clk.h
Kconfig
Makefile