d0a2f82da9
device_type property is bogus, thus use proper compatible. Also change compatible property to "fsl,ucc-mdio". Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
395 lines
9.0 KiB
Plaintext
395 lines
9.0 KiB
Plaintext
/*
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* MPC8323E EMDS Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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* To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
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* this:
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*
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* 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
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* 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
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* next to the serial ports.
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* 3) Solder a wire from U61-22 to P19K-22.
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*
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* Note that there's a typo in the schematic. The board labels the last column
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* of pins "P19K", but in the schematic, that column is called "P19J". So if
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* you're going by the schematic, the pin is called "P19J-K22".
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*/
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/ {
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model = "MPC8323EMDS";
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compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8323@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <4000>; // L1, 16K
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i-cache-size = <4000>; // L1, 16K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 08000000>;
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};
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bcsr@f8000000 {
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device_type = "board-control";
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reg = <f8000000 8000>;
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};
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soc8323@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00000200>;
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bus-frequency = <7DE2900>;
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <200 100>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <e 8>;
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interrupt-parent = < &ipic >;
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dfsrr;
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rtc@68 {
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compatible = "dallas,ds1374";
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reg = <68>;
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>;
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clock-frequency = <0>;
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interrupts = <9 8>;
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interrupt-parent = < &ipic >;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>;
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clock-frequency = <0>;
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interrupts = <a 8>;
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interrupt-parent = < &ipic >;
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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reg = <30000 7000>;
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interrupts = <b 8>;
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interrupt-parent = < &ipic >;
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/* Rev. 2.2 */
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num-channels = <1>;
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channel-fifo-len = <18>;
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exec-units-mask = <0000004c>;
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descriptor-types-mask = <0122003f>;
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};
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ipic: pic@700 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <700 100>;
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device_type = "ipic";
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};
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par_io@1400 {
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reg = <1400 100>;
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device_type = "par_io";
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num-ports = <7>;
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pio3: ucc_pin@03 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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3 4 3 0 2 0 /* MDIO */
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3 5 1 0 2 0 /* MDC */
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0 d 2 0 1 0 /* RX_CLK (CLK9) */
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3 18 2 0 1 0 /* TX_CLK (CLK10) */
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1 0 1 0 1 0 /* TxD0 */
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1 1 1 0 1 0 /* TxD1 */
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1 2 1 0 1 0 /* TxD2 */
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1 3 1 0 1 0 /* TxD3 */
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1 4 2 0 1 0 /* RxD0 */
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1 5 2 0 1 0 /* RxD1 */
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1 6 2 0 1 0 /* RxD2 */
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1 7 2 0 1 0 /* RxD3 */
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1 8 2 0 1 0 /* RX_ER */
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1 9 1 0 1 0 /* TX_ER */
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1 a 2 0 1 0 /* RX_DV */
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1 b 2 0 1 0 /* COL */
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1 c 1 0 1 0 /* TX_EN */
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1 d 2 0 1 0>;/* CRS */
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};
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pio4: ucc_pin@04 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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3 1f 2 0 1 0 /* RX_CLK (CLK7) */
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3 6 2 0 1 0 /* TX_CLK (CLK8) */
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1 12 1 0 1 0 /* TxD0 */
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1 13 1 0 1 0 /* TxD1 */
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1 14 1 0 1 0 /* TxD2 */
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1 15 1 0 1 0 /* TxD3 */
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1 16 2 0 1 0 /* RxD0 */
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1 17 2 0 1 0 /* RxD1 */
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1 18 2 0 1 0 /* RxD2 */
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1 19 2 0 1 0 /* RxD3 */
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1 1a 2 0 1 0 /* RX_ER */
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1 1b 1 0 1 0 /* TX_ER */
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1 1c 2 0 1 0 /* RX_DV */
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1 1d 2 0 1 0 /* COL */
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1 1e 1 0 1 0 /* TX_EN */
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1 1f 2 0 1 0>;/* CRS */
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};
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pio5: ucc_pin@05 {
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pio-map = <
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/*
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* open has
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* port pin dir drain sel irq
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*/
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2 0 1 0 2 0 /* TxD5 */
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2 8 2 0 2 0 /* RxD5 */
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2 1d 2 0 0 0 /* CTS5 */
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2 1f 1 0 2 0 /* RTS5 */
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2 18 2 0 0 0 /* CD */
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>;
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};
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};
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};
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qe@e0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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ranges = <0 e0100000 00100000>;
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reg = <e0100000 480>;
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brg-frequency = <0>;
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bus-frequency = <BCD3D80>;
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muram@10000 {
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0 00010000 00004000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0 4000>;
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};
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};
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spi@4c0 {
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device_type = "spi";
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compatible = "fsl_spi";
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reg = <4c0 40>;
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interrupts = <2>;
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interrupt-parent = < &qeic >;
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mode = "cpu";
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};
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spi@500 {
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device_type = "spi";
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compatible = "fsl_spi";
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reg = <500 40>;
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interrupts = <1>;
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interrupt-parent = < &qeic >;
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mode = "cpu";
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};
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usb@6c0 {
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compatible = "qe_udc";
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reg = <6c0 40 8B00 100>;
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interrupts = <b>;
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interrupt-parent = < &qeic >;
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mode = "slave";
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};
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enet0: ucc@2200 {
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device_type = "network";
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compatible = "ucc_geth";
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model = "UCC";
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cell-index = <3>;
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device-id = <3>;
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reg = <2200 200>;
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interrupts = <22>;
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interrupt-parent = < &qeic >;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "clk9";
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tx-clock-name = "clk10";
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phy-handle = < &phy3 >;
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pio-handle = < &pio3 >;
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};
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enet1: ucc@3200 {
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device_type = "network";
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compatible = "ucc_geth";
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model = "UCC";
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cell-index = <4>;
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device-id = <4>;
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reg = <3200 200>;
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interrupts = <23>;
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interrupt-parent = < &qeic >;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "clk7";
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tx-clock-name = "clk8";
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phy-handle = < &phy4 >;
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pio-handle = < &pio4 >;
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};
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ucc@2400 {
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device_type = "serial";
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compatible = "ucc_uart";
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model = "UCC";
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device-id = <5>; /* The UCC number, 1-7*/
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port-number = <0>; /* Which ttyQEx device */
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soft-uart; /* We need Soft-UART */
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reg = <2400 200>;
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interrupts = <28>; /* From Table 18-12 */
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interrupt-parent = < &qeic >;
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/*
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* For Soft-UART, we need to set TX to 1X, which
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* means specifying separate clock sources.
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*/
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rx-clock-name = "brg5";
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tx-clock-name = "brg6";
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pio-handle = < &pio5 >;
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};
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mdio@2320 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2320 18>;
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compatible = "fsl,ucc-mdio";
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phy3: ethernet-phy@03 {
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interrupt-parent = < &ipic >;
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interrupts = <11 8>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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phy4: ethernet-phy@04 {
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interrupt-parent = < &ipic >;
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interrupts = <12 8>;
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reg = <4>;
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device_type = "ethernet-phy";
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};
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};
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <80 80>;
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big-endian;
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interrupts = <20 8 21 8>; //high:32 low:33
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interrupt-parent = < &ipic >;
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};
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};
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pci0: pci@e0008500 {
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cell-index = <1>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 AD17 */
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8800 0 0 1 &ipic 14 8
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8800 0 0 2 &ipic 15 8
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8800 0 0 3 &ipic 16 8
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8800 0 0 4 &ipic 17 8
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/* IDSEL 0x12 AD18 */
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9000 0 0 1 &ipic 16 8
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9000 0 0 2 &ipic 17 8
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9000 0 0 3 &ipic 14 8
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9000 0 0 4 &ipic 15 8
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/* IDSEL 0x13 AD19 */
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9800 0 0 1 &ipic 17 8
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9800 0 0 2 &ipic 14 8
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9800 0 0 3 &ipic 15 8
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9800 0 0 4 &ipic 16 8
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/* IDSEL 0x15 AD21*/
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a800 0 0 1 &ipic 14 8
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a800 0 0 2 &ipic 15 8
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a800 0 0 3 &ipic 16 8
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a800 0 0 4 &ipic 17 8
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/* IDSEL 0x16 AD22*/
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b000 0 0 1 &ipic 17 8
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b000 0 0 2 &ipic 14 8
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b000 0 0 3 &ipic 15 8
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b000 0 0 4 &ipic 16 8
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/* IDSEL 0x17 AD23*/
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b800 0 0 1 &ipic 16 8
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b800 0 0 2 &ipic 17 8
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b800 0 0 3 &ipic 14 8
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b800 0 0 4 &ipic 15 8
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/* IDSEL 0x18 AD24*/
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c000 0 0 1 &ipic 15 8
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c000 0 0 2 &ipic 16 8
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c000 0 0 3 &ipic 17 8
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c000 0 0 4 &ipic 14 8>;
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interrupt-parent = < &ipic >;
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interrupts = <42 8>;
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bus-range = <0 0>;
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ranges = <02000000 0 90000000 90000000 0 10000000
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42000000 0 80000000 80000000 0 10000000
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01000000 0 00000000 d0000000 0 00100000>;
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clock-frequency = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008500 100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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};
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