a62e90308f
The previous nuc932 support patches have been discarded by me and because it belongs to another SoCs series named nuc93x,at present, which included nuc931 and nuc932, I think it is better to create a new mach-nuc93x,So I made the patch,and request your advice.Thanks! Signed-off-by: Wan ZongShun <mcuos.com@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
/*
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* arch/arm/mach-nuc93x/include/mach/regs-clock.h
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*
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* Copyright (c) 2008 Nuvoton technology corporation.
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*
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* Wan ZongShun <mcuos.com@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation;version 2 of the License.
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*
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*/
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#ifndef __ASM_ARCH_REGS_CLOCK_H
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#define __ASM_ARCH_REGS_CLOCK_H
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/* Clock Control Registers */
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#define CLK_BA NUC93X_VA_CLKPWR
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#define REG_CLKEN (CLK_BA + 0x00)
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#define REG_CLKSEL (CLK_BA + 0x04)
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#define REG_CLKDIV (CLK_BA + 0x08)
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#define REG_PLLCON0 (CLK_BA + 0x0C)
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#define REG_PLLCON1 (CLK_BA + 0x10)
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#define REG_PMCON (CLK_BA + 0x14)
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#define REG_IRQWAKECON (CLK_BA + 0x18)
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#define REG_IRQWAKEFLAG (CLK_BA + 0x1C)
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#define REG_IPSRST (CLK_BA + 0x20)
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#define REG_CLKEN1 (CLK_BA + 0x24)
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#define REG_CLKDIV1 (CLK_BA + 0x28)
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/* Define PLL freq setting */
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#define PLL_DISABLE 0x12B63
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#define PLL_66MHZ 0x2B63
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#define PLL_100MHZ 0x4F64
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#define PLL_120MHZ 0x4F63
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#define PLL_166MHZ 0x4124
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#define PLL_200MHZ 0x4F24
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/* Define AHB:CPUFREQ ratio */
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#define AHB_CPUCLK_1_1 0x00
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#define AHB_CPUCLK_1_2 0x01
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#define AHB_CPUCLK_1_4 0x02
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#define AHB_CPUCLK_1_8 0x03
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/* Define APB:AHB ratio */
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#define APB_AHB_1_2 0x01
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#define APB_AHB_1_4 0x02
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#define APB_AHB_1_8 0x03
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/* Define clock skew */
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#define DEFAULTSKEW 0x48
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#endif /* __ASM_ARCH_REGS_CLOCK_H */
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