43eeb0fb9f
This also fixes up a long-standing bug for this platform where the PIO base was set to a register offset, rather than the actual PIO offset itself. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/*
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* linux/arch/sh/drivers/pci/ops-sh03.c
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*
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* PCI initialization for the Interface CTP/PCI-SH03 board
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#include "pci-sh7751.h"
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/*
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* Description: This function sets up and initializes the pcic, sets
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* up the BARS, maps the DRAM into the address space etc, etc.
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*/
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int __init pcibios_init_platform(void)
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{
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__set_io_port_base(SH7751_PCI_IO_BASE);
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return 1;
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}
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static struct resource sh7751_io_resource = {
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.name = "SH03 IO",
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.start = SH7751_PCI_IO_BASE,
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.end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource sh7751_mem_resource = {
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.name = "SH03 mem",
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.start = SH7751_PCI_MEMORY_BASE,
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.end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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extern struct pci_ops sh4_pci_ops;
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struct pci_channel board_pci_channels[] = {
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{ &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
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{ NULL, NULL, NULL, 0, 0 },
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};
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