382ff806bb
MI2S capture fails on gki build as there are no separate cpu dais for rx and tx. This is due to afe port start opening rx port on capture. Add separate dais for mi2s rx and tx to resolve issue. Change-Id: I37cc1132039ee1525c4f16f8b10b0a9344989d75 Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
117 lines
2.5 KiB
C
117 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2012-2017, 2019, 2021 The Linux Foundation. All rights reserved.
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*/
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#ifndef __MSM_DAI_Q6_PDATA_H__
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#define __MSM_DAI_Q6_PDATA_H__
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#define MSM_MI2S_SD0 (1 << 0)
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#define MSM_MI2S_SD1 (1 << 1)
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#define MSM_MI2S_SD2 (1 << 2)
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#define MSM_MI2S_SD3 (1 << 3)
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#define MSM_MI2S_SD4 (1 << 4)
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#define MSM_MI2S_SD5 (1 << 5)
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#define MSM_MI2S_SD6 (1 << 6)
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#define MSM_MI2S_SD7 (1 << 7)
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#define MSM_MI2S_CAP_RX 0
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#define MSM_MI2S_CAP_TX 1
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#define MSM_PRIM_MI2S_RX 0
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#define MSM_PRIM_MI2S_TX 1
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#define MSM_SEC_MI2S_RX 2
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#define MSM_SEC_MI2S_TX 3
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#define MSM_TERT_MI2S_RX 4
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#define MSM_TERT_MI2S_TX 5
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#define MSM_QUAT_MI2S_RX 6
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#define MSM_QUAT_MI2S_TX 7
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#define MSM_QUIN_MI2S_RX 8
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#define MSM_QUIN_MI2S_TX 9
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#define MSM_SENARY_MI2S_RX 10
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#define MSM_SENARY_MI2S_TX 11
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#define MSM_SEC_MI2S_SD1 12
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#define MSM_INT0_MI2S_RX 13
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#define MSM_INT0_MI2S_TX 14
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#define MSM_INT1_MI2S_RX 15
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#define MSM_INT1_MI2S_TX 16
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#define MSM_INT2_MI2S_RX 17
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#define MSM_INT2_MI2S_TX 18
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#define MSM_INT3_MI2S_RX 19
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#define MSM_INT3_MI2S_TX 20
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#define MSM_INT4_MI2S_RX 21
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#define MSM_INT4_MI2S_TX 22
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#define MSM_INT5_MI2S_RX 23
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#define MSM_INT5_MI2S_TX 24
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#define MSM_INT6_MI2S_RX 25
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#define MSM_INT6_MI2S_TX 26
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#define MSM_MI2S_MIN MSM_PRIM_MI2S_RX
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#define MSM_MI2S_MAX MSM_INT6_MI2S_TX
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#define MSM_DISPLAY_PORT 0
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#define MSM_DISPLAY_PORT1 1
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#define MSM_PRIM_META_MI2S 0
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#define MSM_SEC_META_MI2S 1
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#define MSM_META_MI2S_MIN MSM_PRIM_META_MI2S
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#define MSM_META_MI2S_MAX MSM_SEC_META_MI2S
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struct msm_dai_auxpcm_config {
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u16 mode;
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u16 sync;
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u16 frame;
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u16 quant;
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u16 num_slots;
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u16 *slot_mapping;
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u16 data;
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u32 pcm_clk_rate;
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};
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struct msm_dai_auxpcm_pdata {
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struct msm_dai_auxpcm_config mode_8k;
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struct msm_dai_auxpcm_config mode_16k;
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};
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struct msm_mi2s_pdata {
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u16 sd_lines;
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u16 intf_id;
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};
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struct msm_meta_mi2s_pdata {
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u32 num_member_ports;
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u32 member_port[MAX_NUM_I2S_META_PORT_MEMBER_PORTS];
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u32 sd_lines[MAX_NUM_I2S_META_PORT_MEMBER_PORTS];
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u16 intf_id;
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};
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struct msm_i2s_data {
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u32 capability; /* RX or TX */
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u16 sd_lines;
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};
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struct msm_dai_tdm_group_config {
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u16 group_id;
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u16 num_ports;
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u16 *port_id;
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u32 clk_rate;
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};
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struct msm_dai_tdm_config {
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u16 sync_mode;
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u16 sync_src;
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u16 data_out;
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u16 invert_sync;
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u16 data_delay;
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u32 data_align;
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u16 header_start_offset;
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u16 header_width;
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u16 header_num_frame_repeat;
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};
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struct msm_dai_tdm_pdata {
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struct msm_dai_tdm_group_config group_config;
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struct msm_dai_tdm_config config;
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};
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#endif
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