ae78fd954b
Video kernel snapshot before disabling msm/vidc compilation from base kernel. Change-Id: Id1178c3aca00706ad4822537f7f9a28141478771 Signed-off-by: Shivendra Kakrania <shiven@codeaurora.org>
140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef __HFI_IO_COMMON_H__
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#define __HFI_IO_COMMON_H__
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#include <linux/io.h>
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#define VBIF_BASE_OFFS 0x00080000
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#define CPU_BASE_OFFS 0x000C0000
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#define CPU_CS_BASE_OFFS (CPU_BASE_OFFS + 0x00012000)
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#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS + 0x0001F000)
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#define CPU_CS_A2HSOFTINT (CPU_CS_BASE_OFFS + 0x18)
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#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
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#define CPU_CS_VMIMSG (CPU_CS_BASE_OFFS + 0x34)
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#define CPU_CS_VMIMSGAG0 (CPU_CS_BASE_OFFS + 0x38)
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#define CPU_CS_VMIMSGAG1 (CPU_CS_BASE_OFFS + 0x3C)
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#define CPU_CS_SCIACMD (CPU_CS_BASE_OFFS + 0x48)
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/* HFI_CTRL_STATUS */
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#define CPU_CS_SCIACMDARG0 (CPU_CS_BASE_OFFS + 0x4C)
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#define CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK 0xfe
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#define CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY 0x100
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#define CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK 0x40000000
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/* HFI_QTBL_INFO */
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#define CPU_CS_SCIACMDARG1 (CPU_CS_BASE_OFFS + 0x50)
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/* HFI_QTBL_ADDR */
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#define CPU_CS_SCIACMDARG2 (CPU_CS_BASE_OFFS + 0x54)
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/* HFI_VERSION_INFO */
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#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE_OFFS + 0x58)
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/* SFR_ADDR */
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#define CPU_CS_SCIBCMD (CPU_CS_BASE_OFFS + 0x5C)
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/* MMAP_ADDR */
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#define CPU_CS_SCIBCMDARG0 (CPU_CS_BASE_OFFS + 0x60)
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/* UC_REGION_ADDR */
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#define CPU_CS_SCIBARG1 (CPU_CS_BASE_OFFS + 0x64)
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/* UC_REGION_ADDR */
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#define CPU_CS_SCIBARG2 (CPU_CS_BASE_OFFS + 0x68)
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#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x18)
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#define CPU_IC_SOFTINT_H2A_SHFT 0xF
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/*
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* --------------------------------------------------------------------------
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* MODULE: wrapper
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* --------------------------------------------------------------------------
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*/
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#define WRAPPER_BASE_OFFS 0x000E0000
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#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C)
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#define WRAPPER_INTR_STATUS_A2HWD_BMSK 0x10
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#define WRAPPER_INTR_STATUS_A2H_BMSK 0x4
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#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10)
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#define WRAPPER_INTR_MASK_A2HWD_BMSK 0x10
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#define WRAPPER_INTR_MASK_A2HVCODEC_BMSK 0x8
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#define WRAPPER_INTR_MASK_A2HCPU_BMSK 0x4
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#define WRAPPER_INTR_CLEAR (WRAPPER_BASE_OFFS + 0x14)
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#define WRAPPER_CPU_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x2000)
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#define WRAPPER_CPU_CGC_DIS (WRAPPER_BASE_OFFS + 0x2010)
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#define WRAPPER_CPU_STATUS (WRAPPER_BASE_OFFS + 0x2014)
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#define CTRL_INIT CPU_CS_SCIACMD
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#define CTRL_STATUS CPU_CS_SCIACMDARG0
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#define CTRL_ERROR_STATUS__M \
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CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK
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#define CTRL_INIT_IDLE_MSG_BMSK \
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CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK
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#define CTRL_STATUS_PC_READY \
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CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY
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#define QTBL_INFO CPU_CS_SCIACMDARG1
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#define QTBL_ADDR CPU_CS_SCIACMDARG2
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#define VERSION_INFO CPU_CS_SCIACMDARG3
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#define SFR_ADDR CPU_CS_SCIBCMD
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#define MMAP_ADDR CPU_CS_SCIBCMDARG0
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#define UC_REGION_ADDR CPU_CS_SCIBARG1
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#define UC_REGION_SIZE CPU_CS_SCIBARG2
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/* HFI_DSP_QTBL_ADDR
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* 31:3 - HFI_DSP_QTBL_ADDR
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* 4-byte aligned Address
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*/
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#define HFI_DSP_QTBL_ADDR CPU_CS_VMIMSG
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/* HFI_DSP_UC_REGION_ADDR
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* 31:20 - HFI_DSP_UC_REGION_ADDR
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* 1MB aligned address.
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* Uncached Region start Address. This region covers
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* HFI DSP QTable,
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* HFI DSP Queue Headers,
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* HFI DSP Queues,
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*/
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#define HFI_DSP_UC_REGION_ADDR CPU_CS_VMIMSGAG0
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/* HFI_DSP_UC_REGION_SIZE
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* 31:20 - HFI_DSP_UC_REGION_SIZE
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* Multiples of 1MB.
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* Size of the DSP_UC_REGION Uncached Region
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*/
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#define HFI_DSP_UC_REGION_SIZE CPU_CS_VMIMSGAG1
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/*
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* --------------------------------------------------------------------------
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* MODULE: vcodec noc error log registers
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* --------------------------------------------------------------------------
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*/
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#define VCODEC_CORE0_VIDEO_NOC_BASE_OFFS 0x00004000
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#define VCODEC_CORE1_VIDEO_NOC_BASE_OFFS 0x0000C000
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#define VCODEC_COREX_VIDEO_NOC_ERR_SWID_LOW_OFFS 0x0500
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#define VCODEC_COREX_VIDEO_NOC_ERR_SWID_HIGH_OFFS 0x0504
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#define VCODEC_COREX_VIDEO_NOC_ERR_MAINCTL_LOW_OFFS 0x0508
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#define VCODEC_COREX_VIDEO_NOC_ERR_ERRVLD_LOW_OFFS 0x0510
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#define VCODEC_COREX_VIDEO_NOC_ERR_ERRCLR_LOW_OFFS 0x0518
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#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG0_LOW_OFFS 0x0520
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#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG0_HIGH_OFFS 0x0524
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#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG1_LOW_OFFS 0x0528
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#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG1_HIGH_OFFS 0x052C
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#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG2_LOW_OFFS 0x0530
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#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG2_HIGH_OFFS 0x0534
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#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG3_LOW_OFFS 0x0538
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#define VCODEC_COREX_VIDEO_NOC_ERR_ERRLOG3_HIGH_OFFS 0x053C
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#endif
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