df35f3ef5e
FW common files needs to be in sync with host and fw. Abstract extra definition of hia map internal to hif layer. MSI_NUM_REQUEST is incorrectly overwritten, keep the original change as MSI_ENABLE is false across all target versions. These changes are incorrectly added in following change id. Iced029073c2db9eb175adcebcad9163ab39443a9. Change-Id: Ie38666f315067ae40676e3bdac9238e4b52e6be1 CRs-Fixed: 1012542
106 lines
3.6 KiB
C
106 lines
3.6 KiB
C
/*
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* Copyright (c) 2013-2014, 2016 The Linux Foundation. All rights reserved.
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*
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* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* This file was originally distributed by Qualcomm Atheros, Inc.
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* under proprietary terms before Copyright ownership was assigned
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* to the Linux Foundation.
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*/
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#ifndef __CEPCI_H__
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#define __CEPCI_H__
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/*
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* Support for Copy Engine over PCI.
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* Structures shared between Host software and Target firmware.
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*/
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/*
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* Total number of PCIe MSI interrupts requested for all interrupt sources.
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* PCIe standard forces this to be a power of 2.
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* Some Host OS's limit MSI requests that can be granted to 8
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* so for now we abide by this limit and avoid requesting more
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* than that.
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*/
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#define MSI_NUM_REQUEST_LOG2 3
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#define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2)
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/*
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* Granted MSIs are assigned as follows:
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* Firmware uses the first
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* Remaining MSIs, if any, are used by Copy Engines
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* This mapping is known to both Target firmware and Host software.
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* It may be changed as long as Host and Target are kept in sync.
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*/
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#define MSI_ASSIGN_FW 0 /* 1 MSI for firmware (errors, etc.) */
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#define MSI_ASSIGN_CE_INITIAL 1 /* 7 MSIs for Copy Engines */
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#define MSI_ASSIGN_CE_MAX 7
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/*
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* PCI-specific Target state. Much of this may be of interest
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* to the Host so HOST_INTEREST->hi_interconnect_state points
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* here (and all members are 32-bit quantities in order to
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* facilitate Host access). In particular, Host software is
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* required to initialize pipe_cfg_addr and svc_to_pipe_map.
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*/
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struct pcie_state_s {
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uint32_t pipe_cfg_addr; /* Pipe configuration Target address */
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/* NB: CE_pipe_config[CE_COUNT] */
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uint32_t svc_to_pipe_map; /* Service to pipe map Target address */
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/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
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uint32_t MSI_requested; /* number of MSI interrupts requested */
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uint32_t MSI_granted; /* number of MSI interrupts granted */
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uint32_t MSI_addr; /* Message Signalled Interrupt address */
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uint32_t MSI_data; /* Base data */
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uint32_t MSI_fw_intr_data; /* Data for firmware interrupt;
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MSI data for other interrupts are
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in various SoC registers */
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uint32_t power_mgmt_method; /* PCIE_PWR_METHOD_* */
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uint32_t config_flags; /* PCIE_CONFIG_FLAG_* */
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};
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/*
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* PCIE_CONFIG_FLAG definitions
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*/
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#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
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#define PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT 0x0000002
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#define PCIE_CONFIG_FLAG_AXI_CLK_GATE 0x0000004
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#define PIPE_TO_CE_MAP_CNT 32 /* simple implementation constant */
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/*
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* Configuration information for a Copy Engine pipe.
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* Passed from Host to Target during startup (one per CE).
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*/
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struct CE_pipe_config {
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uint32_t pipenum;
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uint32_t pipedir;
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uint32_t nentries;
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uint32_t nbytes_max;
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uint32_t flags;
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uint32_t reserved;
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};
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#endif /* __CEPCI_H__ */
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