3aa630b3e6
Remove trailing semicolon from register-access macros. Signed-off-by: Johan Hovold <jhovold@gmail.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
54 lines
1.9 KiB
C
54 lines
1.9 KiB
C
/*
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* arch/arm/mach-at91/include/mach/at91_rstc.h
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*
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* Copyright (C) 2007 Andrew Victor
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* Copyright (C) 2007 Atmel Corporation.
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*
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* Reset Controller (RSTC) - System peripherals regsters.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_RSTC_H
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#define AT91_RSTC_H
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#ifndef __ASSEMBLY__
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extern void __iomem *at91_rstc_base;
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#define at91_rstc_read(field) \
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__raw_readl(at91_rstc_base + field)
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#define at91_rstc_write(field, value) \
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__raw_writel(value, at91_rstc_base + field)
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#else
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.extern at91_rstc_base
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#endif
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#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
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#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
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#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
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#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
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#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
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#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
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#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
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#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
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#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
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#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
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#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
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#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
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#define AT91_RSTC_RSTTYP_USER (4 << 8)
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#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
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#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
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#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
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#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
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#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
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#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
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#endif
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