cebf589c82
Add support for the integrated interrupt controller on BPA CPUs. There is one of those for each SMT thread. The mapping of interrupt numbers to HW interrupt sources is described in arch/ppc64/kernel/bpa_iic.h. This version hardcodes the 'Spider' chip as the secondary interrupt controller. That is not really generic for the architecture, but at the moment it is the only secondary PIC that exists. A little more work will be needed on this as soon as we have boards with multiple external interrupt controllers. Signed-off-by: Arnd Bergmann <arndb@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
#ifndef ASM_BPA_IIC_H
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#define ASM_BPA_IIC_H
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#ifdef __KERNEL__
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/*
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* Mapping of IIC pending bits into per-node
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* interrupt numbers.
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*
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* IRQ FF CC SS PP FF CC SS PP Description
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*
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* 00-3f 80 02 +0 00 - 80 02 +0 3f South Bridge
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* 00-3f 80 02 +b 00 - 80 02 +b 3f South Bridge
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* 41-4a 80 00 +1 ** - 80 00 +a ** SPU Class 0
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* 51-5a 80 01 +1 ** - 80 01 +a ** SPU Class 1
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* 61-6a 80 02 +1 ** - 80 02 +a ** SPU Class 2
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* 70-7f C0 ** ** 00 - C0 ** ** 0f IPI
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*
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* F flags
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* C class
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* S source
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* P Priority
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* + node number
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* * don't care
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*
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* A node consists of a Broadband Engine and an optional
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* south bridge device providing a maximum of 64 IRQs.
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* The south bridge may be connected to either IOIF0
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* or IOIF1.
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* Each SPE is represented as three IRQ lines, one per
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* interrupt class.
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* 16 IRQ numbers are reserved for inter processor
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* interruptions, although these are only used in the
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* range of the first node.
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*
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* This scheme needs 128 IRQ numbers per BIF node ID,
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* which means that with the total of 512 lines
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* available, we can have a maximum of four nodes.
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*/
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enum {
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IIC_EXT_OFFSET = 0x00, /* Start of south bridge IRQs */
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IIC_NUM_EXT = 0x40, /* Number of south bridge IRQs */
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IIC_SPE_OFFSET = 0x40, /* Start of SPE interrupts */
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IIC_CLASS_STRIDE = 0x10, /* SPE IRQs per class */
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IIC_IPI_OFFSET = 0x70, /* Start of IPI IRQs */
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IIC_NUM_IPIS = 0x10, /* IRQs reserved for IPI */
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IIC_NODE_STRIDE = 0x80, /* Total IRQs per node */
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};
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extern void iic_init_IRQ(void);
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extern int iic_get_irq(struct pt_regs *regs);
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extern void iic_cause_IPI(int cpu, int mesg);
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extern void iic_request_IPIs(void);
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extern void iic_setup_cpu(void);
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extern void iic_local_enable(void);
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extern void iic_local_disable(void);
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extern void spider_init_IRQ(void);
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extern int spider_get_irq(unsigned long int_pending);
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#endif
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#endif /* ASM_BPA_IIC_H */
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