192 lines
4.9 KiB
C
192 lines
4.9 KiB
C
#ifndef __ASM_SH_SYSTEM_H
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#define __ASM_SH_SYSTEM_H
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/*
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* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
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* Copyright (C) 2002 Paul Mundt
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*/
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#include <linux/irqflags.h>
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#include <linux/compiler.h>
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#include <linux/linkage.h>
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#include <asm/types.h>
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#include <asm/ptrace.h>
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#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
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#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
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#define __icbi() \
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{ \
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unsigned long __addr; \
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__addr = 0xa8000000; \
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__asm__ __volatile__( \
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"icbi %0\n\t" \
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: /* no output */ \
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: "m" (__m(__addr))); \
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}
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#endif
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/*
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* A brief note on ctrl_barrier(), the control register write barrier.
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*
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* Legacy SH cores typically require a sequence of 8 nops after
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* modification of a control register in order for the changes to take
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* effect. On newer cores (like the sh4a and sh5) this is accomplished
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* with icbi.
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*
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* Also note that on sh4a in the icbi case we can forego a synco for the
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* write barrier, as it's not necessary for control registers.
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*
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* Historically we have only done this type of barrier for the MMUCR, but
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* it's also necessary for the CCR, so we make it generic here instead.
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*/
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#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
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#define mb() __asm__ __volatile__ ("synco": : :"memory")
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#define rmb() mb()
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#define wmb() __asm__ __volatile__ ("synco": : :"memory")
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#define ctrl_barrier() __icbi()
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#define read_barrier_depends() do { } while(0)
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#else
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#define mb() __asm__ __volatile__ ("": : :"memory")
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#define rmb() mb()
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#define wmb() __asm__ __volatile__ ("": : :"memory")
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#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
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#define read_barrier_depends() do { } while(0)
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#endif
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#endif
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#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#ifdef CONFIG_GUSA_RB
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#include <asm/cmpxchg-grb.h>
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#else
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#include <asm/cmpxchg-irq.h>
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#endif
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extern void __xchg_called_with_bad_pointer(void);
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#define __xchg(ptr, x, size) \
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({ \
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unsigned long __xchg__res; \
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volatile void *__xchg_ptr = (ptr); \
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switch (size) { \
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case 4: \
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__xchg__res = xchg_u32(__xchg_ptr, x); \
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break; \
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case 1: \
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__xchg__res = xchg_u8(__xchg_ptr, x); \
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break; \
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default: \
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__xchg_called_with_bad_pointer(); \
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__xchg__res = x; \
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break; \
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} \
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\
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__xchg__res; \
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})
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#define xchg(ptr,x) \
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((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
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/* This function doesn't exist, so you'll get a linker error
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* if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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#define __HAVE_ARCH_CMPXCHG 1
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static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,o,n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
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extern void *set_exception_table_vec(unsigned int vec, void *handler);
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static inline void *set_exception_table_evt(unsigned int evt, void *handler)
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{
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return set_exception_table_vec(evt >> 5, handler);
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}
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/*
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* SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
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*/
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#ifdef CONFIG_CPU_SH2A
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extern unsigned int instruction_size(unsigned int insn);
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#elif defined(CONFIG_SUPERH32)
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#define instruction_size(insn) (2)
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#else
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#define instruction_size(insn) (4)
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#endif
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extern unsigned long cached_to_uncached;
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/* XXX
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* disable hlt during certain critical i/o operations
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*/
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#define HAVE_DISABLE_HLT
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void disable_hlt(void);
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void enable_hlt(void);
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void default_idle(void);
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void per_cpu_trap_init(void);
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asmlinkage void break_point_trap(void);
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#ifdef CONFIG_SUPERH32
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#define BUILD_TRAP_HANDLER(name) \
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asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
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unsigned long r6, unsigned long r7, \
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struct pt_regs __regs)
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#define TRAP_HANDLER_DECL \
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struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \
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unsigned int vec = regs->tra; \
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(void)vec;
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#else
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#define BUILD_TRAP_HANDLER(name) \
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asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
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#define TRAP_HANDLER_DECL
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#endif
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BUILD_TRAP_HANDLER(address_error);
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BUILD_TRAP_HANDLER(debug);
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BUILD_TRAP_HANDLER(bug);
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BUILD_TRAP_HANDLER(fpu_error);
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BUILD_TRAP_HANDLER(fpu_state_restore);
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#define arch_align_stack(x) (x)
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#ifdef CONFIG_SUPERH32
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# include "system_32.h"
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#else
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# include "system_64.h"
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#endif
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#endif
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