71e0b484a1
Lito has three data lanes for tx swr. As gpio support for swr tx data3 is present for lito v2, enable data lane for lito v2. Change-Id: I56faee1974f59e0a506fc74f2dadb95a52071907 Signed-off-by: Vatsal Bucha <vbucha@codeaurora.org>
77 lines
2.8 KiB
C
77 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _KONA_PORT_CONFIG
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#define _KONA_PORT_CONFIG
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#include <soc/swr-common.h>
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#define WSA_MSTR_PORT_MASK 0xFF
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/*
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* Add port configuration in the format
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*{ si, off1, off2, hstart, hstop, wd_len, bp_mode, bgp_ctrl, lane_ctrl}
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*/
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static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
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{7, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},
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{31, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},
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{63, 12, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF},
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{7, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},
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{31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},
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{63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF},
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{15, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},
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{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},
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};
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static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = {
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{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1},
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{31, 0, 0, 3, 6, 7, 0, 0xFF, 0},
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{31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0},
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{7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0},
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{0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0},
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};
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static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
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{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1},
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{31, 0, 0, 3, 6, 7, 0, 0xFF, 0},
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{31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0},
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{7, 9, 0, 0xFF, 0xFF, 0xFF, 0xFF, 1, 0},
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{3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0},
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};
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/* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */
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static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = {
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},/* PCM OUT */
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{1, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX1 */
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{1, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1}, /* TX2 */
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{3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX3 */
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{3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1}, /* TX4 */
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};
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/* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */
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static struct port_params tx_frame_params_v2[SWR_MSTR_PORT_LEN] = {
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{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF},/* PCM OUT */
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{1, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1}, /* TX1 */
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{1, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 2}, /* TX2 */
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{3, 2, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX3 */
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{3, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 2}, /* TX4 */
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};
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static struct swr_mstr_port_map sm_port_map[] = {
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{TX_MACRO, SWR_UC0, tx_frame_params_default},
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{RX_MACRO, SWR_UC0, rx_frame_params_default},
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{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
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{WSA_MACRO, SWR_UC0, wsa_frame_params_default},
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};
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static struct swr_mstr_port_map sm_port_map_v2[] = {
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{TX_MACRO, SWR_UC0, tx_frame_params_v2},
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{RX_MACRO, SWR_UC0, rx_frame_params_default},
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{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
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{WSA_MACRO, SWR_UC0, wsa_frame_params_default},
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};
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#endif /* _KONA_PORT_CONFIG */
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