585cf17561
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces, and, depending on the specific model, PCI-E interface, PCI-X interface, SATA controllers, crypto unit, SPI interface, SDIO interface, device bus, NAND controller, DMA engine and/or XOR engine. This contains the basic structure and architecture register definitions. Signed-off-by: Tzachi Perelstein <tzachi@marvell.com> Reviewed-by: Nicolas Pitre <nico@marvell.com> Reviewed-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
62 lines
1.5 KiB
C
62 lines
1.5 KiB
C
/*
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* include/asm-arm/arch-orion/irqs.h
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*
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* IRQ definitions for Orion SoC
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_IRQS_H__
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#define __ASM_ARCH_IRQS_H__
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#include "orion.h" /* need GPIO_MAX */
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/*
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* Orion Main Interrupt Controller
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*/
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#define IRQ_ORION_BRIDGE 0
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#define IRQ_ORION_DOORBELL_H2C 1
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#define IRQ_ORION_DOORBELL_C2H 2
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#define IRQ_ORION_UART0 3
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#define IRQ_ORION_UART1 4
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#define IRQ_ORION_I2C 5
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#define IRQ_ORION_GPIO_0_7 6
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#define IRQ_ORION_GPIO_8_15 7
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#define IRQ_ORION_GPIO_16_23 8
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#define IRQ_ORION_GPIO_24_31 9
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#define IRQ_ORION_PCIE0_ERR 10
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#define IRQ_ORION_PCIE0_INT 11
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#define IRQ_ORION_USB1_CTRL 12
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#define IRQ_ORION_DEV_BUS_ERR 14
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#define IRQ_ORION_PCI_ERR 15
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#define IRQ_ORION_USB_BR_ERR 16
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#define IRQ_ORION_USB0_CTRL 17
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#define IRQ_ORION_ETH_RX 18
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#define IRQ_ORION_ETH_TX 19
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#define IRQ_ORION_ETH_MISC 20
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#define IRQ_ORION_ETH_SUM 21
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#define IRQ_ORION_ETH_ERR 22
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#define IRQ_ORION_IDMA_ERR 23
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#define IRQ_ORION_IDMA_0 24
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#define IRQ_ORION_IDMA_1 25
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#define IRQ_ORION_IDMA_2 26
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#define IRQ_ORION_IDMA_3 27
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#define IRQ_ORION_CESA 28
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#define IRQ_ORION_SATA 29
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#define IRQ_ORION_XOR0 30
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#define IRQ_ORION_XOR1 31
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/*
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* Orion General Purpose Pins
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*/
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#define IRQ_ORION_GPIO_START 32
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#define NR_GPIO_IRQS GPIO_MAX
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#define NR_IRQS (IRQ_ORION_GPIO_START + NR_GPIO_IRQS)
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#endif /* __ASM_ARCH_IRQS_H__ */
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