38b33707a1
The CCK and OFDM ANI error triggers are not mode specific but rather band specific so just make use of the already available band from ieee80211_conf. Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
849 lines
24 KiB
C
849 lines
24 KiB
C
/*
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* Copyright (c) 2008 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "core.h"
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#include "hw.h"
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#include "reg.h"
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#include "phy.h"
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static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
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struct ath9k_channel *chan)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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int i;
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for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
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if (ahp->ah_ani[i].c.channel == chan->channel)
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return i;
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if (ahp->ah_ani[i].c.channel == 0) {
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ahp->ah_ani[i].c.channel = chan->channel;
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ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
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return i;
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}
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}
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"No more channel states left. Using channel 0\n");
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return 0;
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}
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static bool ath9k_hw_ani_control(struct ath_hal *ah,
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enum ath9k_ani_cmd cmd, int param)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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struct ar5416AniState *aniState = ahp->ah_curani;
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switch (cmd & ahp->ah_ani_function) {
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case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
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u32 level = param;
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if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"level out of range (%u > %u)\n",
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level,
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(unsigned)ARRAY_SIZE(ahp->ah_totalSizeDesired));
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return false;
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}
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REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
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AR_PHY_DESIRED_SZ_TOT_DES,
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ahp->ah_totalSizeDesired[level]);
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REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
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AR_PHY_AGC_CTL1_COARSE_LOW,
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ahp->ah_coarseLow[level]);
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REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
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AR_PHY_AGC_CTL1_COARSE_HIGH,
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ahp->ah_coarseHigh[level]);
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REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
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AR_PHY_FIND_SIG_FIRPWR,
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ahp->ah_firpwr[level]);
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if (level > aniState->noiseImmunityLevel)
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ahp->ah_stats.ast_ani_niup++;
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else if (level < aniState->noiseImmunityLevel)
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ahp->ah_stats.ast_ani_nidown++;
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aniState->noiseImmunityLevel = level;
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break;
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}
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case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
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const int m1ThreshLow[] = { 127, 50 };
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const int m2ThreshLow[] = { 127, 40 };
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const int m1Thresh[] = { 127, 0x4d };
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const int m2Thresh[] = { 127, 0x40 };
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const int m2CountThr[] = { 31, 16 };
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const int m2CountThrLow[] = { 63, 48 };
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u32 on = param ? 1 : 0;
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
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m1ThreshLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
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m2ThreshLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR,
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AR_PHY_SFCORR_M1_THRESH,
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m1Thresh[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR,
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AR_PHY_SFCORR_M2_THRESH,
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m2Thresh[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR,
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AR_PHY_SFCORR_M2COUNT_THR,
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m2CountThr[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
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m2CountThrLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
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AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
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m1ThreshLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
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AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
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m2ThreshLow[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
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AR_PHY_SFCORR_EXT_M1_THRESH,
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m1Thresh[on]);
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REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
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AR_PHY_SFCORR_EXT_M2_THRESH,
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m2Thresh[on]);
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if (on)
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REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
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else
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REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
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AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
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if (!on != aniState->ofdmWeakSigDetectOff) {
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if (on)
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ahp->ah_stats.ast_ani_ofdmon++;
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else
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ahp->ah_stats.ast_ani_ofdmoff++;
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aniState->ofdmWeakSigDetectOff = !on;
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}
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break;
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}
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case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
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const int weakSigThrCck[] = { 8, 6 };
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u32 high = param ? 1 : 0;
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REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
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AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
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weakSigThrCck[high]);
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if (high != aniState->cckWeakSigThreshold) {
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if (high)
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ahp->ah_stats.ast_ani_cckhigh++;
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else
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ahp->ah_stats.ast_ani_ccklow++;
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aniState->cckWeakSigThreshold = high;
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}
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break;
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}
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case ATH9K_ANI_FIRSTEP_LEVEL:{
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const int firstep[] = { 0, 4, 8 };
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u32 level = param;
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if (level >= ARRAY_SIZE(firstep)) {
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"level out of range (%u > %u)\n",
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level,
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(unsigned) ARRAY_SIZE(firstep));
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return false;
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}
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REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
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AR_PHY_FIND_SIG_FIRSTEP,
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firstep[level]);
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if (level > aniState->firstepLevel)
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ahp->ah_stats.ast_ani_stepup++;
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else if (level < aniState->firstepLevel)
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ahp->ah_stats.ast_ani_stepdown++;
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aniState->firstepLevel = level;
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break;
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}
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case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
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const int cycpwrThr1[] =
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{ 2, 4, 6, 8, 10, 12, 14, 16 };
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u32 level = param;
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if (level >= ARRAY_SIZE(cycpwrThr1)) {
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"level out of range (%u > %u)\n",
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level,
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(unsigned)
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ARRAY_SIZE(cycpwrThr1));
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return false;
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}
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REG_RMW_FIELD(ah, AR_PHY_TIMING5,
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AR_PHY_TIMING5_CYCPWR_THR1,
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cycpwrThr1[level]);
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if (level > aniState->spurImmunityLevel)
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ahp->ah_stats.ast_ani_spurup++;
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else if (level < aniState->spurImmunityLevel)
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ahp->ah_stats.ast_ani_spurdown++;
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aniState->spurImmunityLevel = level;
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break;
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}
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case ATH9K_ANI_PRESENT:
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break;
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default:
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"invalid cmd %u\n", cmd);
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return false;
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}
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DPRINTF(ah->ah_sc, ATH_DBG_ANI, "ANI parameters:\n");
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"noiseImmunityLevel=%d, spurImmunityLevel=%d, "
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"ofdmWeakSigDetectOff=%d\n",
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aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
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!aniState->ofdmWeakSigDetectOff);
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"cckWeakSigThreshold=%d, "
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"firstepLevel=%d, listenTime=%d\n",
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aniState->cckWeakSigThreshold, aniState->firstepLevel,
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aniState->listenTime);
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
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aniState->cycleCount, aniState->ofdmPhyErrCount,
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aniState->cckPhyErrCount);
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return true;
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}
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static void ath9k_hw_update_mibstats(struct ath_hal *ah,
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struct ath9k_mib_stats *stats)
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{
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stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
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stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
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stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
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stats->rts_good += REG_READ(ah, AR_RTS_OK);
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stats->beacons += REG_READ(ah, AR_BEACON_CNT);
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}
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static void ath9k_ani_restart(struct ath_hal *ah)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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struct ar5416AniState *aniState;
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if (!DO_ANI(ah))
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return;
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aniState = ahp->ah_curani;
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aniState->listenTime = 0;
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if (ahp->ah_hasHwPhyCounters) {
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if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
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aniState->ofdmPhyErrBase = 0;
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"OFDM Trigger is too high for hw counters\n");
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} else {
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aniState->ofdmPhyErrBase =
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AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
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}
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if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
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aniState->cckPhyErrBase = 0;
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"CCK Trigger is too high for hw counters\n");
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} else {
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aniState->cckPhyErrBase =
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AR_PHY_COUNTMAX - aniState->cckTrigHigh;
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}
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DPRINTF(ah->ah_sc, ATH_DBG_ANI,
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"Writing ofdmbase=%u cckbase=%u\n",
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aniState->ofdmPhyErrBase,
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aniState->cckPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
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REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
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REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
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ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
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}
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aniState->ofdmPhyErrCount = 0;
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aniState->cckPhyErrCount = 0;
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}
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static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
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struct ar5416AniState *aniState;
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int32_t rssi;
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if (!DO_ANI(ah))
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return;
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aniState = ahp->ah_curani;
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if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
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if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
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aniState->noiseImmunityLevel + 1)) {
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return;
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}
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}
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if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
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if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
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aniState->spurImmunityLevel + 1)) {
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return;
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}
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}
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if (ah->ah_opmode == NL80211_IFTYPE_AP) {
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if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel + 1);
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}
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return;
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}
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rssi = BEACON_RSSI(ahp);
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if (rssi > aniState->rssiThrHigh) {
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if (!aniState->ofdmWeakSigDetectOff) {
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if (ath9k_hw_ani_control(ah,
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ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
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false)) {
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ath9k_hw_ani_control(ah,
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ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
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return;
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}
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}
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if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel + 1);
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return;
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}
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} else if (rssi > aniState->rssiThrLow) {
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if (aniState->ofdmWeakSigDetectOff)
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ath9k_hw_ani_control(ah,
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ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
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true);
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if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel + 1);
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return;
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} else {
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if (conf->channel->band == IEEE80211_BAND_2GHZ) {
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if (!aniState->ofdmWeakSigDetectOff)
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ath9k_hw_ani_control(ah,
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ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
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false);
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if (aniState->firstepLevel > 0)
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ath9k_hw_ani_control(ah,
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ATH9K_ANI_FIRSTEP_LEVEL, 0);
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return;
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}
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}
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}
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static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
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struct ar5416AniState *aniState;
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int32_t rssi;
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if (!DO_ANI(ah))
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return;
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aniState = ahp->ah_curani;
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if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
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if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
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aniState->noiseImmunityLevel + 1)) {
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return;
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}
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}
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if (ah->ah_opmode == NL80211_IFTYPE_AP) {
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if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel + 1);
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}
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return;
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}
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rssi = BEACON_RSSI(ahp);
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if (rssi > aniState->rssiThrLow) {
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if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
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ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel + 1);
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} else {
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if (conf->channel->band == IEEE80211_BAND_2GHZ) {
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if (aniState->firstepLevel > 0)
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ath9k_hw_ani_control(ah,
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ATH9K_ANI_FIRSTEP_LEVEL, 0);
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}
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}
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}
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static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
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{
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struct ath_hal_5416 *ahp = AH5416(ah);
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struct ar5416AniState *aniState;
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int32_t rssi;
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aniState = ahp->ah_curani;
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if (ah->ah_opmode == NL80211_IFTYPE_AP) {
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if (aniState->firstepLevel > 0) {
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if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel - 1))
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return;
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}
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} else {
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rssi = BEACON_RSSI(ahp);
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if (rssi > aniState->rssiThrHigh) {
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/* XXX: Handle me */
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} else if (rssi > aniState->rssiThrLow) {
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if (aniState->ofdmWeakSigDetectOff) {
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if (ath9k_hw_ani_control(ah,
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ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
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true) == true)
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return;
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}
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if (aniState->firstepLevel > 0) {
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if (ath9k_hw_ani_control(ah,
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ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel - 1) == true)
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return;
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}
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} else {
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if (aniState->firstepLevel > 0) {
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if (ath9k_hw_ani_control(ah,
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ATH9K_ANI_FIRSTEP_LEVEL,
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aniState->firstepLevel - 1) == true)
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return;
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}
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}
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}
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if (aniState->spurImmunityLevel > 0) {
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if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
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aniState->spurImmunityLevel - 1))
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return;
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}
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if (aniState->noiseImmunityLevel > 0) {
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ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
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aniState->noiseImmunityLevel - 1);
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return;
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}
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}
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|
|
static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
struct ar5416AniState *aniState;
|
|
u32 txFrameCount, rxFrameCount, cycleCount;
|
|
int32_t listenTime;
|
|
|
|
txFrameCount = REG_READ(ah, AR_TFCNT);
|
|
rxFrameCount = REG_READ(ah, AR_RFCNT);
|
|
cycleCount = REG_READ(ah, AR_CCCNT);
|
|
|
|
aniState = ahp->ah_curani;
|
|
if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
|
|
|
|
listenTime = 0;
|
|
ahp->ah_stats.ast_ani_lzero++;
|
|
} else {
|
|
int32_t ccdelta = cycleCount - aniState->cycleCount;
|
|
int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
|
|
int32_t tfdelta = txFrameCount - aniState->txFrameCount;
|
|
listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
|
|
}
|
|
aniState->cycleCount = cycleCount;
|
|
aniState->txFrameCount = txFrameCount;
|
|
aniState->rxFrameCount = rxFrameCount;
|
|
|
|
return listenTime;
|
|
}
|
|
|
|
void ath9k_ani_reset(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
struct ar5416AniState *aniState;
|
|
struct ath9k_channel *chan = ah->ah_curchan;
|
|
int index;
|
|
|
|
if (!DO_ANI(ah))
|
|
return;
|
|
|
|
index = ath9k_hw_get_ani_channel_idx(ah, chan);
|
|
aniState = &ahp->ah_ani[index];
|
|
ahp->ah_curani = aniState;
|
|
|
|
if (DO_ANI(ah) && ah->ah_opmode != NL80211_IFTYPE_STATION
|
|
&& ah->ah_opmode != NL80211_IFTYPE_ADHOC) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
|
|
"Reset ANI state opmode %u\n", ah->ah_opmode);
|
|
ahp->ah_stats.ast_ani_reset++;
|
|
|
|
ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
|
|
ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
|
|
ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
|
|
ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
|
|
!ATH9K_ANI_USE_OFDM_WEAK_SIG);
|
|
ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
|
|
ATH9K_ANI_CCK_WEAK_SIG_THR);
|
|
|
|
ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
|
|
ATH9K_RX_FILTER_PHYERR);
|
|
|
|
if (ah->ah_opmode == NL80211_IFTYPE_AP) {
|
|
ahp->ah_curani->ofdmTrigHigh =
|
|
ah->ah_config.ofdm_trig_high;
|
|
ahp->ah_curani->ofdmTrigLow =
|
|
ah->ah_config.ofdm_trig_low;
|
|
ahp->ah_curani->cckTrigHigh =
|
|
ah->ah_config.cck_trig_high;
|
|
ahp->ah_curani->cckTrigLow =
|
|
ah->ah_config.cck_trig_low;
|
|
}
|
|
ath9k_ani_restart(ah);
|
|
return;
|
|
}
|
|
|
|
if (aniState->noiseImmunityLevel != 0)
|
|
ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
|
|
aniState->noiseImmunityLevel);
|
|
if (aniState->spurImmunityLevel != 0)
|
|
ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
|
|
aniState->spurImmunityLevel);
|
|
if (aniState->ofdmWeakSigDetectOff)
|
|
ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
|
|
!aniState->ofdmWeakSigDetectOff);
|
|
if (aniState->cckWeakSigThreshold)
|
|
ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
|
|
aniState->cckWeakSigThreshold);
|
|
if (aniState->firstepLevel != 0)
|
|
ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
|
|
aniState->firstepLevel);
|
|
if (ahp->ah_hasHwPhyCounters) {
|
|
ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
|
|
~ATH9K_RX_FILTER_PHYERR);
|
|
ath9k_ani_restart(ah);
|
|
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
|
|
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
|
|
|
|
} else {
|
|
ath9k_ani_restart(ah);
|
|
ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
|
|
ATH9K_RX_FILTER_PHYERR);
|
|
}
|
|
}
|
|
|
|
void ath9k_hw_ani_monitor(struct ath_hal *ah,
|
|
const struct ath9k_node_stats *stats,
|
|
struct ath9k_channel *chan)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
struct ar5416AniState *aniState;
|
|
int32_t listenTime;
|
|
|
|
aniState = ahp->ah_curani;
|
|
ahp->ah_stats.ast_nodestats = *stats;
|
|
|
|
listenTime = ath9k_hw_ani_get_listen_time(ah);
|
|
if (listenTime < 0) {
|
|
ahp->ah_stats.ast_ani_lneg++;
|
|
ath9k_ani_restart(ah);
|
|
return;
|
|
}
|
|
|
|
aniState->listenTime += listenTime;
|
|
|
|
if (ahp->ah_hasHwPhyCounters) {
|
|
u32 phyCnt1, phyCnt2;
|
|
u32 ofdmPhyErrCnt, cckPhyErrCnt;
|
|
|
|
ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
|
|
|
|
phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
|
|
phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
|
|
|
|
if (phyCnt1 < aniState->ofdmPhyErrBase ||
|
|
phyCnt2 < aniState->cckPhyErrBase) {
|
|
if (phyCnt1 < aniState->ofdmPhyErrBase) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
|
|
"phyCnt1 0x%x, resetting "
|
|
"counter value to 0x%x\n",
|
|
phyCnt1,
|
|
aniState->ofdmPhyErrBase);
|
|
REG_WRITE(ah, AR_PHY_ERR_1,
|
|
aniState->ofdmPhyErrBase);
|
|
REG_WRITE(ah, AR_PHY_ERR_MASK_1,
|
|
AR_PHY_ERR_OFDM_TIMING);
|
|
}
|
|
if (phyCnt2 < aniState->cckPhyErrBase) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
|
|
"phyCnt2 0x%x, resetting "
|
|
"counter value to 0x%x\n",
|
|
phyCnt2,
|
|
aniState->cckPhyErrBase);
|
|
REG_WRITE(ah, AR_PHY_ERR_2,
|
|
aniState->cckPhyErrBase);
|
|
REG_WRITE(ah, AR_PHY_ERR_MASK_2,
|
|
AR_PHY_ERR_CCK_TIMING);
|
|
}
|
|
return;
|
|
}
|
|
|
|
ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
|
|
ahp->ah_stats.ast_ani_ofdmerrs +=
|
|
ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
|
|
aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
|
|
|
|
cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
|
|
ahp->ah_stats.ast_ani_cckerrs +=
|
|
cckPhyErrCnt - aniState->cckPhyErrCount;
|
|
aniState->cckPhyErrCount = cckPhyErrCnt;
|
|
}
|
|
|
|
if (!DO_ANI(ah))
|
|
return;
|
|
|
|
if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
|
|
if (aniState->ofdmPhyErrCount <= aniState->listenTime *
|
|
aniState->ofdmTrigLow / 1000 &&
|
|
aniState->cckPhyErrCount <= aniState->listenTime *
|
|
aniState->cckTrigLow / 1000)
|
|
ath9k_hw_ani_lower_immunity(ah);
|
|
ath9k_ani_restart(ah);
|
|
} else if (aniState->listenTime > ahp->ah_aniPeriod) {
|
|
if (aniState->ofdmPhyErrCount > aniState->listenTime *
|
|
aniState->ofdmTrigHigh / 1000) {
|
|
ath9k_hw_ani_ofdm_err_trigger(ah);
|
|
ath9k_ani_restart(ah);
|
|
} else if (aniState->cckPhyErrCount >
|
|
aniState->listenTime * aniState->cckTrigHigh /
|
|
1000) {
|
|
ath9k_hw_ani_cck_err_trigger(ah);
|
|
ath9k_ani_restart(ah);
|
|
}
|
|
}
|
|
}
|
|
|
|
bool ath9k_hw_phycounters(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
|
|
return ahp->ah_hasHwPhyCounters ? true : false;
|
|
}
|
|
|
|
void ath9k_enable_mib_counters(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n");
|
|
|
|
ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
|
|
|
|
REG_WRITE(ah, AR_FILT_OFDM, 0);
|
|
REG_WRITE(ah, AR_FILT_CCK, 0);
|
|
REG_WRITE(ah, AR_MIBC,
|
|
~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
|
|
& 0x0f);
|
|
REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
|
|
REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
|
|
}
|
|
|
|
void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n");
|
|
|
|
REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
|
|
|
|
ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
|
|
|
|
REG_WRITE(ah, AR_FILT_OFDM, 0);
|
|
REG_WRITE(ah, AR_FILT_CCK, 0);
|
|
}
|
|
|
|
u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
|
|
u32 *rxc_pcnt,
|
|
u32 *rxf_pcnt,
|
|
u32 *txf_pcnt)
|
|
{
|
|
static u32 cycles, rx_clear, rx_frame, tx_frame;
|
|
u32 good = 1;
|
|
|
|
u32 rc = REG_READ(ah, AR_RCCNT);
|
|
u32 rf = REG_READ(ah, AR_RFCNT);
|
|
u32 tf = REG_READ(ah, AR_TFCNT);
|
|
u32 cc = REG_READ(ah, AR_CCCNT);
|
|
|
|
if (cycles == 0 || cycles > cc) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
|
|
"cycle counter wrap. ExtBusy = 0\n");
|
|
good = 0;
|
|
} else {
|
|
u32 cc_d = cc - cycles;
|
|
u32 rc_d = rc - rx_clear;
|
|
u32 rf_d = rf - rx_frame;
|
|
u32 tf_d = tf - tx_frame;
|
|
|
|
if (cc_d != 0) {
|
|
*rxc_pcnt = rc_d * 100 / cc_d;
|
|
*rxf_pcnt = rf_d * 100 / cc_d;
|
|
*txf_pcnt = tf_d * 100 / cc_d;
|
|
} else {
|
|
good = 0;
|
|
}
|
|
}
|
|
|
|
cycles = cc;
|
|
rx_frame = rf;
|
|
rx_clear = rc;
|
|
tx_frame = tf;
|
|
|
|
return good;
|
|
}
|
|
|
|
/*
|
|
* Process a MIB interrupt. We may potentially be invoked because
|
|
* any of the MIB counters overflow/trigger so don't assume we're
|
|
* here because a PHY error counter triggered.
|
|
*/
|
|
void ath9k_hw_procmibevent(struct ath_hal *ah,
|
|
const struct ath9k_node_stats *stats)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
u32 phyCnt1, phyCnt2;
|
|
|
|
/* Reset these counters regardless */
|
|
REG_WRITE(ah, AR_FILT_OFDM, 0);
|
|
REG_WRITE(ah, AR_FILT_CCK, 0);
|
|
if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
|
|
REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
|
|
|
|
/* Clear the mib counters and save them in the stats */
|
|
ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
|
|
ahp->ah_stats.ast_nodestats = *stats;
|
|
|
|
if (!DO_ANI(ah))
|
|
return;
|
|
|
|
/* NB: these are not reset-on-read */
|
|
phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
|
|
phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
|
|
if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
|
|
((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
|
|
struct ar5416AniState *aniState = ahp->ah_curani;
|
|
u32 ofdmPhyErrCnt, cckPhyErrCnt;
|
|
|
|
/* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
|
|
ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
|
|
ahp->ah_stats.ast_ani_ofdmerrs +=
|
|
ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
|
|
aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
|
|
|
|
cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
|
|
ahp->ah_stats.ast_ani_cckerrs +=
|
|
cckPhyErrCnt - aniState->cckPhyErrCount;
|
|
aniState->cckPhyErrCount = cckPhyErrCnt;
|
|
|
|
/*
|
|
* NB: figure out which counter triggered. If both
|
|
* trigger we'll only deal with one as the processing
|
|
* clobbers the error counter so the trigger threshold
|
|
* check will never be true.
|
|
*/
|
|
if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
|
|
ath9k_hw_ani_ofdm_err_trigger(ah);
|
|
if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
|
|
ath9k_hw_ani_cck_err_trigger(ah);
|
|
/* NB: always restart to insure the h/w counters are reset */
|
|
ath9k_ani_restart(ah);
|
|
}
|
|
}
|
|
|
|
void ath9k_hw_ani_setup(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
int i;
|
|
|
|
const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
|
|
const int coarseHigh[] = { -14, -14, -14, -14, -12 };
|
|
const int coarseLow[] = { -64, -64, -64, -64, -70 };
|
|
const int firpwr[] = { -78, -78, -78, -78, -80 };
|
|
|
|
for (i = 0; i < 5; i++) {
|
|
ahp->ah_totalSizeDesired[i] = totalSizeDesired[i];
|
|
ahp->ah_coarseHigh[i] = coarseHigh[i];
|
|
ahp->ah_coarseLow[i] = coarseLow[i];
|
|
ahp->ah_firpwr[i] = firpwr[i];
|
|
}
|
|
}
|
|
|
|
void ath9k_hw_ani_attach(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
int i;
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Attach ANI\n");
|
|
|
|
ahp->ah_hasHwPhyCounters = 1;
|
|
|
|
memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
|
|
for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
|
|
ahp->ah_ani[i].ofdmTrigHigh = ATH9K_ANI_OFDM_TRIG_HIGH;
|
|
ahp->ah_ani[i].ofdmTrigLow = ATH9K_ANI_OFDM_TRIG_LOW;
|
|
ahp->ah_ani[i].cckTrigHigh = ATH9K_ANI_CCK_TRIG_HIGH;
|
|
ahp->ah_ani[i].cckTrigLow = ATH9K_ANI_CCK_TRIG_LOW;
|
|
ahp->ah_ani[i].rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
|
|
ahp->ah_ani[i].rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
|
|
ahp->ah_ani[i].ofdmWeakSigDetectOff =
|
|
!ATH9K_ANI_USE_OFDM_WEAK_SIG;
|
|
ahp->ah_ani[i].cckWeakSigThreshold =
|
|
ATH9K_ANI_CCK_WEAK_SIG_THR;
|
|
ahp->ah_ani[i].spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
|
|
ahp->ah_ani[i].firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
|
|
if (ahp->ah_hasHwPhyCounters) {
|
|
ahp->ah_ani[i].ofdmPhyErrBase =
|
|
AR_PHY_COUNTMAX - ATH9K_ANI_OFDM_TRIG_HIGH;
|
|
ahp->ah_ani[i].cckPhyErrBase =
|
|
AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
|
|
}
|
|
}
|
|
if (ahp->ah_hasHwPhyCounters) {
|
|
DPRINTF(ah->ah_sc, ATH_DBG_ANI,
|
|
"Setting OfdmErrBase = 0x%08x\n",
|
|
ahp->ah_ani[0].ofdmPhyErrBase);
|
|
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
|
|
ahp->ah_ani[0].cckPhyErrBase);
|
|
|
|
REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
|
|
REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
|
|
ath9k_enable_mib_counters(ah);
|
|
}
|
|
ahp->ah_aniPeriod = ATH9K_ANI_PERIOD;
|
|
if (ah->ah_config.enable_ani)
|
|
ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
|
|
}
|
|
|
|
void ath9k_hw_ani_detach(struct ath_hal *ah)
|
|
{
|
|
struct ath_hal_5416 *ahp = AH5416(ah);
|
|
|
|
DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Detach ANI\n");
|
|
|
|
if (ahp->ah_hasHwPhyCounters) {
|
|
ath9k_hw_disable_mib_counters(ah);
|
|
REG_WRITE(ah, AR_PHY_ERR_1, 0);
|
|
REG_WRITE(ah, AR_PHY_ERR_2, 0);
|
|
}
|
|
}
|