2b94397adc
Run the existing ehca code through checkpatch.pl and clean up the worst of the coding style violations. Signed-off-by: Joachim Fenkes <fenkes@de.ibm.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
410 lines
8.6 KiB
C
410 lines
8.6 KiB
C
/*
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* IBM eServer eHCA Infiniband device driver for Linux on POWER
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*
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* eHCA register definitions
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*
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* Authors: Waleri Fomin <fomin@de.ibm.com>
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* Christoph Raisch <raisch@de.ibm.com>
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* Reinhard Ernst <rernst@de.ibm.com>
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*
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* Copyright (c) 2005 IBM Corporation
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*
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* All rights reserved.
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*
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* This source code is distributed under a dual license of GPL v2.0 and OpenIB
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* BSD.
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*
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* OpenIB BSD License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials
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* provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __HIPZ_HW_H__
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#define __HIPZ_HW_H__
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#include "ehca_tools.h"
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#define EHCA_MAX_MTU 4
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/* QP Table Entry Memory Map */
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struct hipz_qptemm {
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u64 qpx_hcr;
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u64 qpx_c;
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u64 qpx_herr;
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u64 qpx_aer;
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/* 0x20*/
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u64 qpx_sqa;
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u64 qpx_sqc;
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u64 qpx_rqa;
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u64 qpx_rqc;
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/* 0x40*/
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u64 qpx_st;
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u64 qpx_pmstate;
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u64 qpx_pmfa;
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u64 qpx_pkey;
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/* 0x60*/
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u64 qpx_pkeya;
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u64 qpx_pkeyb;
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u64 qpx_pkeyc;
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u64 qpx_pkeyd;
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/* 0x80*/
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u64 qpx_qkey;
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u64 qpx_dqp;
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u64 qpx_dlidp;
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u64 qpx_portp;
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/* 0xa0*/
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u64 qpx_slidp;
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u64 qpx_slidpp;
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u64 qpx_dlida;
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u64 qpx_porta;
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/* 0xc0*/
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u64 qpx_slida;
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u64 qpx_slidpa;
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u64 qpx_slvl;
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u64 qpx_ipd;
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/* 0xe0*/
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u64 qpx_mtu;
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u64 qpx_lato;
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u64 qpx_rlimit;
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u64 qpx_rnrlimit;
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/* 0x100*/
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u64 qpx_t;
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u64 qpx_sqhp;
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u64 qpx_sqptp;
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u64 qpx_nspsn;
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/* 0x120*/
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u64 qpx_nspsnhwm;
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u64 reserved1;
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u64 qpx_sdsi;
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u64 qpx_sdsbc;
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/* 0x140*/
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u64 qpx_sqwsize;
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u64 qpx_sqwts;
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u64 qpx_lsn;
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u64 qpx_nssn;
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/* 0x160 */
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u64 qpx_mor;
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u64 qpx_cor;
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u64 qpx_sqsize;
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u64 qpx_erc;
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/* 0x180*/
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u64 qpx_rnrrc;
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u64 qpx_ernrwt;
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u64 qpx_rnrresp;
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u64 qpx_lmsna;
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/* 0x1a0 */
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u64 qpx_sqhpc;
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u64 qpx_sqcptp;
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u64 qpx_sigt;
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u64 qpx_wqecnt;
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/* 0x1c0*/
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u64 qpx_rqhp;
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u64 qpx_rqptp;
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u64 qpx_rqsize;
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u64 qpx_nrr;
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/* 0x1e0*/
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u64 qpx_rdmac;
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u64 qpx_nrpsn;
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u64 qpx_lapsn;
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u64 qpx_lcr;
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/* 0x200*/
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u64 qpx_rwc;
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u64 qpx_rwva;
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u64 qpx_rdsi;
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u64 qpx_rdsbc;
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/* 0x220*/
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u64 qpx_rqwsize;
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u64 qpx_crmsn;
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u64 qpx_rdd;
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u64 qpx_larpsn;
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/* 0x240*/
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u64 qpx_pd;
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u64 qpx_scqn;
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u64 qpx_rcqn;
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u64 qpx_aeqn;
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/* 0x260*/
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u64 qpx_aaelog;
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u64 qpx_ram;
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u64 qpx_rdmaqe0;
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u64 qpx_rdmaqe1;
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/* 0x280*/
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u64 qpx_rdmaqe2;
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u64 qpx_rdmaqe3;
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u64 qpx_nrpsnhwm;
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/* 0x298*/
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u64 reserved[(0x400 - 0x298) / 8];
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/* 0x400 extended data */
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u64 reserved_ext[(0x500 - 0x400) / 8];
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/* 0x500 */
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u64 reserved2[(0x1000 - 0x500) / 8];
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/* 0x1000 */
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};
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#define QPX_SQADDER EHCA_BMASK_IBM(48, 63)
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#define QPX_RQADDER EHCA_BMASK_IBM(48, 63)
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#define QPX_AAELOG_RESET_SRQ_LIMIT EHCA_BMASK_IBM(3, 3)
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#define QPTEMM_OFFSET(x) offsetof(struct hipz_qptemm, x)
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/* MRMWPT Entry Memory Map */
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struct hipz_mrmwmm {
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/* 0x00 */
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u64 mrx_hcr;
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u64 mrx_c;
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u64 mrx_herr;
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u64 mrx_aer;
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/* 0x20 */
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u64 mrx_pp;
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u64 reserved1;
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u64 reserved2;
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u64 reserved3;
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/* 0x40 */
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u64 reserved4[(0x200 - 0x40) / 8];
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/* 0x200 */
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u64 mrx_ctl[64];
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};
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#define MRMWMM_OFFSET(x) offsetof(struct hipz_mrmwmm, x)
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struct hipz_qpedmm {
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/* 0x00 */
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u64 reserved0[(0x400) / 8];
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/* 0x400 */
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u64 qpedx_phh;
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u64 qpedx_ppsgp;
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/* 0x410 */
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u64 qpedx_ppsgu;
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u64 qpedx_ppdgp;
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/* 0x420 */
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u64 qpedx_ppdgu;
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u64 qpedx_aph;
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/* 0x430 */
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u64 qpedx_apsgp;
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u64 qpedx_apsgu;
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/* 0x440 */
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u64 qpedx_apdgp;
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u64 qpedx_apdgu;
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/* 0x450 */
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u64 qpedx_apav;
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u64 qpedx_apsav;
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/* 0x460 */
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u64 qpedx_hcr;
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u64 reserved1[4];
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/* 0x488 */
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u64 qpedx_rrl0;
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/* 0x490 */
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u64 qpedx_rrrkey0;
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u64 qpedx_rrva0;
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/* 0x4a0 */
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u64 reserved2;
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u64 qpedx_rrl1;
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/* 0x4b0 */
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u64 qpedx_rrrkey1;
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u64 qpedx_rrva1;
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/* 0x4c0 */
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u64 reserved3;
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u64 qpedx_rrl2;
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/* 0x4d0 */
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u64 qpedx_rrrkey2;
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u64 qpedx_rrva2;
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/* 0x4e0 */
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u64 reserved4;
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u64 qpedx_rrl3;
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/* 0x4f0 */
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u64 qpedx_rrrkey3;
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u64 qpedx_rrva3;
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};
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#define QPEDMM_OFFSET(x) offsetof(struct hipz_qpedmm, x)
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/* CQ Table Entry Memory Map */
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struct hipz_cqtemm {
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u64 cqx_hcr;
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u64 cqx_c;
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u64 cqx_herr;
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u64 cqx_aer;
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/* 0x20 */
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u64 cqx_ptp;
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u64 cqx_tp;
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u64 cqx_fec;
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u64 cqx_feca;
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/* 0x40 */
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u64 cqx_ep;
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u64 cqx_eq;
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/* 0x50 */
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u64 reserved1;
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u64 cqx_n0;
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/* 0x60 */
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u64 cqx_n1;
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u64 reserved2[(0x1000 - 0x60) / 8];
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/* 0x1000 */
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};
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#define CQX_FEC_CQE_CNT EHCA_BMASK_IBM(32, 63)
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#define CQX_FECADDER EHCA_BMASK_IBM(32, 63)
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#define CQX_N0_GENERATE_SOLICITED_COMP_EVENT EHCA_BMASK_IBM(0, 0)
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#define CQX_N1_GENERATE_COMP_EVENT EHCA_BMASK_IBM(0, 0)
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#define CQTEMM_OFFSET(x) offsetof(struct hipz_cqtemm, x)
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/* EQ Table Entry Memory Map */
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struct hipz_eqtemm {
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u64 eqx_hcr;
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u64 eqx_c;
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u64 eqx_herr;
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u64 eqx_aer;
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/* 0x20 */
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u64 eqx_ptp;
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u64 eqx_tp;
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u64 eqx_ssba;
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u64 eqx_psba;
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/* 0x40 */
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u64 eqx_cec;
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u64 eqx_meql;
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u64 eqx_xisbi;
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u64 eqx_xisc;
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/* 0x60 */
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u64 eqx_it;
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};
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#define EQTEMM_OFFSET(x) offsetof(struct hipz_eqtemm, x)
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/* access control defines for MR/MW */
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#define HIPZ_ACCESSCTRL_L_WRITE 0x00800000
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#define HIPZ_ACCESSCTRL_R_WRITE 0x00400000
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#define HIPZ_ACCESSCTRL_R_READ 0x00200000
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#define HIPZ_ACCESSCTRL_R_ATOMIC 0x00100000
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#define HIPZ_ACCESSCTRL_MW_BIND 0x00080000
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/* query hca response block */
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struct hipz_query_hca {
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u32 cur_reliable_dg;
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u32 cur_qp;
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u32 cur_cq;
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u32 cur_eq;
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u32 cur_mr;
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u32 cur_mw;
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u32 cur_ee_context;
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u32 cur_mcast_grp;
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u32 cur_qp_attached_mcast_grp;
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u32 reserved1;
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u32 cur_ipv6_qp;
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u32 cur_eth_qp;
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u32 cur_hp_mr;
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u32 reserved2[3];
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u32 max_rd_domain;
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u32 max_qp;
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u32 max_cq;
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u32 max_eq;
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u32 max_mr;
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u32 max_hp_mr;
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u32 max_mw;
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u32 max_mrwpte;
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u32 max_special_mrwpte;
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u32 max_rd_ee_context;
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u32 max_mcast_grp;
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u32 max_total_mcast_qp_attach;
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u32 max_mcast_qp_attach;
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u32 max_raw_ipv6_qp;
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u32 max_raw_ethy_qp;
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u32 internal_clock_frequency;
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u32 max_pd;
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u32 max_ah;
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u32 max_cqe;
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u32 max_wqes_wq;
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u32 max_partitions;
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u32 max_rr_ee_context;
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u32 max_rr_qp;
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u32 max_rr_hca;
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u32 max_act_wqs_ee_context;
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u32 max_act_wqs_qp;
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u32 max_sge;
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u32 max_sge_rd;
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u32 memory_page_size_supported;
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u64 max_mr_size;
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u32 local_ca_ack_delay;
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u32 num_ports;
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u32 vendor_id;
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u32 vendor_part_id;
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u32 hw_ver;
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u64 node_guid;
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u64 hca_cap_indicators;
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u32 data_counter_register_size;
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u32 max_shared_rq;
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u32 max_isns_eq;
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u32 max_neq;
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} __attribute__ ((packed));
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#define HCA_CAP_AH_PORT_NR_CHECK EHCA_BMASK_IBM( 0, 0)
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#define HCA_CAP_ATOMIC EHCA_BMASK_IBM( 1, 1)
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#define HCA_CAP_AUTO_PATH_MIG EHCA_BMASK_IBM( 2, 2)
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#define HCA_CAP_BAD_P_KEY_CTR EHCA_BMASK_IBM( 3, 3)
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#define HCA_CAP_SQD_RTS_PORT_CHANGE EHCA_BMASK_IBM( 4, 4)
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#define HCA_CAP_CUR_QP_STATE_MOD EHCA_BMASK_IBM( 5, 5)
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#define HCA_CAP_INIT_TYPE EHCA_BMASK_IBM( 6, 6)
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#define HCA_CAP_PORT_ACTIVE_EVENT EHCA_BMASK_IBM( 7, 7)
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#define HCA_CAP_Q_KEY_VIOL_CTR EHCA_BMASK_IBM( 8, 8)
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#define HCA_CAP_WQE_RESIZE EHCA_BMASK_IBM( 9, 9)
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#define HCA_CAP_RAW_PACKET_MCAST EHCA_BMASK_IBM(10, 10)
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#define HCA_CAP_SHUTDOWN_PORT EHCA_BMASK_IBM(11, 11)
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#define HCA_CAP_RC_LL_QP EHCA_BMASK_IBM(12, 12)
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#define HCA_CAP_SRQ EHCA_BMASK_IBM(13, 13)
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#define HCA_CAP_UD_LL_QP EHCA_BMASK_IBM(16, 16)
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#define HCA_CAP_RESIZE_MR EHCA_BMASK_IBM(17, 17)
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#define HCA_CAP_MINI_QP EHCA_BMASK_IBM(18, 18)
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/* query port response block */
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struct hipz_query_port {
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u32 state;
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u32 bad_pkey_cntr;
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u32 lmc;
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u32 lid;
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u32 subnet_timeout;
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u32 qkey_viol_cntr;
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u32 sm_sl;
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u32 sm_lid;
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u32 capability_mask;
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u32 init_type_reply;
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u32 pkey_tbl_len;
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u32 gid_tbl_len;
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u64 gid_prefix;
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u32 port_nr;
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u16 pkey_entries[16];
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u8 reserved1[32];
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u32 trent_size;
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u32 trbuf_size;
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u64 max_msg_sz;
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u32 max_mtu;
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u32 vl_cap;
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u8 reserved2[1900];
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u64 guid_entries[255];
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} __attribute__ ((packed));
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#endif
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