e998f245c4
T3 hardware doorbell FIFO overflows can cause application stalls due to lost doorbell ring events. This has been seen when running large NP IMB alltoall MPI jobs. The T3 hardware supports an xon/xoff-type flow control mechanism to help avoid overflowing the HW doorbell FIFO. This patch uses these interrupts to disable RDMA QP doorbell rings when we near an overflow condition, and then turn them back on (and ring all the active QP doorbells) when when the doorbell FIFO empties out. In addition if an doorbell ring is dropped by the hardware, the code will now recover. Design: cxgb3: - enable these DB interrupts - in the interrupt handler, schedule work tasks to call the ULPs event handlers with the new events. - ring all the qset txqs when an overflow is detected. iw_cxgb3: - disable db ringing on all active qps when we get the DB_FULL event - enable db ringing on all active qps and ring all active dbs when we get the DB_EMPTY event - On DB_DROP event: - disable db rings in the event handler - delay-schedule a work task which rings and enables the dbs on all active qps. - in post_send and post_recv logic, don't ring the db if it's disabled. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Roland Dreier <rolandd@cisco.com>
183 lines
4.6 KiB
C
183 lines
4.6 KiB
C
/*
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* Copyright (c) 2006 Chelsio, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __IWCH_H__
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#define __IWCH_H__
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#include <linux/mutex.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/idr.h>
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#include <linux/workqueue.h>
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#include <rdma/ib_verbs.h>
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#include "cxio_hal.h"
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#include "cxgb3_offload.h"
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struct iwch_pd;
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struct iwch_cq;
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struct iwch_qp;
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struct iwch_mr;
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struct iwch_rnic_attributes {
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u32 max_qps;
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u32 max_wrs; /* Max for any SQ/RQ */
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u32 max_sge_per_wr;
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u32 max_sge_per_rdma_write_wr; /* for RDMA Write WR */
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u32 max_cqs;
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u32 max_cqes_per_cq;
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u32 max_mem_regs;
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u32 max_phys_buf_entries; /* for phys buf list */
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u32 max_pds;
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/*
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* The memory page sizes supported by this RNIC.
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* Bit position i in bitmap indicates page of
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* size (4k)^i. Phys block list mode unsupported.
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*/
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u32 mem_pgsizes_bitmask;
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u64 max_mr_size;
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u8 can_resize_wq;
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/*
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* The maximum number of RDMA Reads that can be outstanding
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* per QP with this RNIC as the target.
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*/
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u32 max_rdma_reads_per_qp;
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/*
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* The maximum number of resources used for RDMA Reads
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* by this RNIC with this RNIC as the target.
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*/
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u32 max_rdma_read_resources;
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/*
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* The max depth per QP for initiation of RDMA Read
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* by this RNIC.
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*/
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u32 max_rdma_read_qp_depth;
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/*
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* The maximum depth for initiation of RDMA Read
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* operations by this RNIC on all QPs
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*/
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u32 max_rdma_read_depth;
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u8 rq_overflow_handled;
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u32 can_modify_ird;
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u32 can_modify_ord;
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u32 max_mem_windows;
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u32 stag0_value;
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u8 zbva_support;
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u8 local_invalidate_fence;
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u32 cq_overflow_detection;
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};
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struct iwch_dev {
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struct ib_device ibdev;
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struct cxio_rdev rdev;
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u32 device_cap_flags;
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struct iwch_rnic_attributes attr;
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struct idr cqidr;
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struct idr qpidr;
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struct idr mmidr;
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spinlock_t lock;
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struct list_head entry;
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struct delayed_work db_drop_task;
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};
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static inline struct iwch_dev *to_iwch_dev(struct ib_device *ibdev)
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{
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return container_of(ibdev, struct iwch_dev, ibdev);
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}
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static inline struct iwch_dev *rdev_to_iwch_dev(struct cxio_rdev *rdev)
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{
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return container_of(rdev, struct iwch_dev, rdev);
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}
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static inline int t3b_device(const struct iwch_dev *rhp)
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{
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return rhp->rdev.t3cdev_p->type == T3B;
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}
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static inline int t3a_device(const struct iwch_dev *rhp)
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{
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return rhp->rdev.t3cdev_p->type == T3A;
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}
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static inline struct iwch_cq *get_chp(struct iwch_dev *rhp, u32 cqid)
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{
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return idr_find(&rhp->cqidr, cqid);
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}
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static inline struct iwch_qp *get_qhp(struct iwch_dev *rhp, u32 qpid)
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{
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return idr_find(&rhp->qpidr, qpid);
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}
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static inline struct iwch_mr *get_mhp(struct iwch_dev *rhp, u32 mmid)
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{
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return idr_find(&rhp->mmidr, mmid);
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}
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static inline int insert_handle(struct iwch_dev *rhp, struct idr *idr,
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void *handle, u32 id)
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{
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int ret;
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int newid;
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do {
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if (!idr_pre_get(idr, GFP_KERNEL)) {
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return -ENOMEM;
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}
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spin_lock_irq(&rhp->lock);
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ret = idr_get_new_above(idr, handle, id, &newid);
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BUG_ON(newid != id);
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spin_unlock_irq(&rhp->lock);
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} while (ret == -EAGAIN);
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return ret;
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}
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static inline void remove_handle(struct iwch_dev *rhp, struct idr *idr, u32 id)
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{
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spin_lock_irq(&rhp->lock);
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idr_remove(idr, id);
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spin_unlock_irq(&rhp->lock);
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}
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extern struct cxgb3_client t3c_client;
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extern cxgb3_cpl_handler_func t3c_handlers[NUM_CPL_CMDS];
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extern void iwch_ev_dispatch(struct cxio_rdev *rdev_p, struct sk_buff *skb);
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#endif
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