619b6e18fc
This complements the generic R4000/R4400 errata workaround code and adds bits for the daddiu problem. In most places it just modifies handwritten assembly code so that the assembler is allowed to use a temporary register as daddiu may now be treated as a macro that expands to a sequence of li and daddu. It is the AT register or, where AT is unavailable or used explicitly for another purpose, an explicitly-named register is selected, using the .set at=<reg> feature added recently to gas. This feature is only used if CONFIG_CPU_DADDI_WORKAROUNDS has been set, so if the workaround remains disabled, the required version of binutils stays unchanged. Similarly, daddiu instructions put in branch delay slots in noreorder fragments are now taken out of them and the assembler is allowed to reorder them itself as possible (which it does making the whole idea of scheduling them into delay slots manually questionable). Also in the very few places where such a simple conversion was not possible, a handcoded longer sequence is implemented. Other than that there are changes to code responsible for building the TLB fault and page clear/copy handlers to avoid daddiu as appropriate. These are only effective if the erratum is verified to be present at the run time. Finally there is a trivial update to __delay(), because it uses daddiu in a branch delay slot. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
500 lines
11 KiB
ArmAsm
500 lines
11 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2001 MIPS Technologies, Inc.
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* Copyright (C) 2002, 2007 Maciej W. Rozycki
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*/
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#include <linux/init.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/cacheops.h>
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#include <asm/irqflags.h>
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#include <asm/regdef.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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#include <asm/war.h>
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#include <asm/page.h>
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#define PANIC_PIC(msg) \
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.set push; \
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.set reorder; \
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PTR_LA a0,8f; \
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.set noat; \
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PTR_LA AT, panic; \
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jr AT; \
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9: b 9b; \
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.set pop; \
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TEXT(msg)
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__INIT
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NESTED(except_vec0_generic, 0, sp)
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PANIC_PIC("Exception vector 0 called")
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END(except_vec0_generic)
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NESTED(except_vec1_generic, 0, sp)
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PANIC_PIC("Exception vector 1 called")
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END(except_vec1_generic)
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/*
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* General exception vector for all other CPUs.
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*
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* Be careful when changing this, it has to be at most 128 bytes
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* to fit into space reserved for the exception handler.
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*/
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NESTED(except_vec3_generic, 0, sp)
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.set push
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.set noat
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#if R5432_CP0_INTERRUPT_WAR
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mfc0 k0, CP0_INDEX
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#endif
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mfc0 k1, CP0_CAUSE
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andi k1, k1, 0x7c
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#ifdef CONFIG_64BIT
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dsll k1, k1, 1
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#endif
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PTR_L k0, exception_handlers(k1)
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jr k0
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.set pop
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END(except_vec3_generic)
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/*
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* General exception handler for CPUs with virtual coherency exception.
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*
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* Be careful when changing this, it has to be at most 256 (as a special
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* exception) bytes to fit into space reserved for the exception handler.
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*/
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NESTED(except_vec3_r4000, 0, sp)
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.set push
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.set mips3
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.set noat
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mfc0 k1, CP0_CAUSE
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li k0, 31<<2
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andi k1, k1, 0x7c
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.set push
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.set noreorder
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.set nomacro
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beq k1, k0, handle_vced
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li k0, 14<<2
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beq k1, k0, handle_vcei
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#ifdef CONFIG_64BIT
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dsll k1, k1, 1
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#endif
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.set pop
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PTR_L k0, exception_handlers(k1)
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jr k0
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/*
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* Big shit, we now may have two dirty primary cache lines for the same
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* physical address. We can safely invalidate the line pointed to by
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* c0_badvaddr because after return from this exception handler the
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* load / store will be re-executed.
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*/
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handle_vced:
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MFC0 k0, CP0_BADVADDR
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li k1, -4 # Is this ...
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and k0, k1 # ... really needed?
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mtc0 zero, CP0_TAGLO
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cache Index_Store_Tag_D, (k0)
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cache Hit_Writeback_Inv_SD, (k0)
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#ifdef CONFIG_PROC_FS
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PTR_LA k0, vced_count
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lw k1, (k0)
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addiu k1, 1
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sw k1, (k0)
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#endif
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eret
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handle_vcei:
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MFC0 k0, CP0_BADVADDR
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cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
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#ifdef CONFIG_PROC_FS
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PTR_LA k0, vcei_count
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lw k1, (k0)
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addiu k1, 1
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sw k1, (k0)
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#endif
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eret
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.set pop
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END(except_vec3_r4000)
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__FINIT
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.align 5
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NESTED(handle_int, PT_SIZE, sp)
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#ifdef CONFIG_TRACE_IRQFLAGS
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/*
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* Check to see if the interrupted code has just disabled
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* interrupts and ignore this interrupt for now if so.
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*
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* local_irq_disable() disables interrupts and then calls
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* trace_hardirqs_off() to track the state. If an interrupt is taken
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* after interrupts are disabled but before the state is updated
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* it will appear to restore_all that it is incorrectly returning with
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* interrupts disabled
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*/
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.set push
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.set noat
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mfc0 k0, CP0_STATUS
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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and k0, ST0_IEP
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bnez k0, 1f
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mfc0 k0, CP0_EPC
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.set noreorder
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j k0
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rfe
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#else
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and k0, ST0_IE
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bnez k0, 1f
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eret
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#endif
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1:
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.set pop
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#endif
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SAVE_ALL
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CLI
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TRACE_IRQS_OFF
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LONG_L s0, TI_REGS($28)
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LONG_S sp, TI_REGS($28)
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PTR_LA ra, ret_from_irq
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j plat_irq_dispatch
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END(handle_int)
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__INIT
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/*
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* Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
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* This is a dedicated interrupt exception vector which reduces the
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* interrupt processing overhead. The jump instruction will be replaced
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* at the initialization time.
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*
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* Be careful when changing this, it has to be at most 128 bytes
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* to fit into space reserved for the exception handler.
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*/
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NESTED(except_vec4, 0, sp)
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1: j 1b /* Dummy, will be replaced */
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END(except_vec4)
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/*
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* EJTAG debug exception handler.
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* The EJTAG debug exception entry point is 0xbfc00480, which
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* normally is in the boot PROM, so the boot PROM must do a
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* unconditional jump to this vector.
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*/
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NESTED(except_vec_ejtag_debug, 0, sp)
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j ejtag_debug_handler
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END(except_vec_ejtag_debug)
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__FINIT
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/*
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* Vectored interrupt handler.
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* This prototype is copied to ebase + n*IntCtl.VS and patched
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* to invoke the handler
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*/
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NESTED(except_vec_vi, 0, sp)
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SAVE_SOME
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SAVE_AT
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.set push
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.set noreorder
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* To keep from blindly blocking *all* interrupts
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* during service by SMTC kernel, we also want to
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* pass the IM value to be cleared.
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*/
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FEXPORT(except_vec_vi_mori)
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ori a0, $0, 0
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#endif /* CONFIG_MIPS_MT_SMTC */
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FEXPORT(except_vec_vi_lui)
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lui v0, 0 /* Patched */
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j except_vec_vi_handler
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FEXPORT(except_vec_vi_ori)
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ori v0, 0 /* Patched */
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.set pop
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END(except_vec_vi)
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EXPORT(except_vec_vi_end)
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/*
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* Common Vectored Interrupt code
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* Complete the register saves and invoke the handler which is passed in $v0
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*/
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NESTED(except_vec_vi_handler, 0, sp)
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SAVE_TEMP
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SAVE_STATIC
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* SMTC has an interesting problem that interrupts are level-triggered,
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* and the CLI macro will clear EXL, potentially causing a duplicate
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* interrupt service invocation. So we need to clear the associated
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* IM bit of Status prior to doing CLI, and restore it after the
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* service routine has been invoked - we must assume that the
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* service routine will have cleared the state, and any active
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* level represents a new or otherwised unserviced event...
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*/
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mfc0 t1, CP0_STATUS
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and t0, a0, t1
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#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
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mfc0 t2, CP0_TCCONTEXT
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or t0, t0, t2
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mtc0 t0, CP0_TCCONTEXT
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#endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
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xor t1, t1, t0
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mtc0 t1, CP0_STATUS
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_ehb
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#endif /* CONFIG_MIPS_MT_SMTC */
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CLI
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#ifdef CONFIG_TRACE_IRQFLAGS
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move s0, v0
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#ifdef CONFIG_MIPS_MT_SMTC
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move s1, a0
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#endif
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TRACE_IRQS_OFF
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#ifdef CONFIG_MIPS_MT_SMTC
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move a0, s1
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#endif
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move v0, s0
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#endif
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LONG_L s0, TI_REGS($28)
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LONG_S sp, TI_REGS($28)
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PTR_LA ra, ret_from_irq
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jr v0
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END(except_vec_vi_handler)
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/*
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* EJTAG debug exception handler.
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*/
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NESTED(ejtag_debug_handler, PT_SIZE, sp)
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.set push
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.set noat
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MTC0 k0, CP0_DESAVE
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mfc0 k0, CP0_DEBUG
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sll k0, k0, 30 # Check for SDBBP.
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bgez k0, ejtag_return
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PTR_LA k0, ejtag_debug_buffer
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LONG_S k1, 0(k0)
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SAVE_ALL
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move a0, sp
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jal ejtag_exception_handler
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RESTORE_ALL
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PTR_LA k0, ejtag_debug_buffer
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LONG_L k1, 0(k0)
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ejtag_return:
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MFC0 k0, CP0_DESAVE
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.set mips32
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deret
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.set pop
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END(ejtag_debug_handler)
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/*
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* This buffer is reserved for the use of the EJTAG debug
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* handler.
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*/
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.data
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EXPORT(ejtag_debug_buffer)
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.fill LONGSIZE
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.previous
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__INIT
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/*
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* NMI debug exception handler for MIPS reference boards.
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* The NMI debug exception entry point is 0xbfc00000, which
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* normally is in the boot PROM, so the boot PROM must do a
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* unconditional jump to this vector.
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*/
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NESTED(except_vec_nmi, 0, sp)
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j nmi_handler
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END(except_vec_nmi)
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__FINIT
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NESTED(nmi_handler, PT_SIZE, sp)
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.set push
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.set noat
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SAVE_ALL
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move a0, sp
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jal nmi_exception_handler
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RESTORE_ALL
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.set mips3
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eret
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.set pop
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END(nmi_handler)
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.macro __build_clear_none
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.endm
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.macro __build_clear_sti
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TRACE_IRQS_ON
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STI
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.endm
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.macro __build_clear_cli
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CLI
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TRACE_IRQS_OFF
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.endm
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.macro __build_clear_fpe
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cfc1 a1, fcr31
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li a2, ~(0x3f << 12)
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and a2, a1
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ctc1 a2, fcr31
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TRACE_IRQS_ON
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STI
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.endm
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.macro __build_clear_ade
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MFC0 t0, CP0_BADVADDR
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PTR_S t0, PT_BVADDR(sp)
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KMODE
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.endm
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.macro __BUILD_silent exception
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.endm
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/* Gas tries to parse the PRINT argument as a string containing
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string escapes and emits bogus warnings if it believes to
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recognize an unknown escape code. So make the arguments
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start with an n and gas will believe \n is ok ... */
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.macro __BUILD_verbose nexception
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LONG_L a1, PT_EPC(sp)
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#ifdef CONFIG_32BIT
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PRINT("Got \nexception at %08lx\012")
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#endif
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#ifdef CONFIG_64BIT
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PRINT("Got \nexception at %016lx\012")
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#endif
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.endm
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.macro __BUILD_count exception
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LONG_L t0,exception_count_\exception
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LONG_ADDIU t0, 1
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LONG_S t0,exception_count_\exception
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.comm exception_count\exception, 8, 8
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.endm
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.macro __BUILD_HANDLER exception handler clear verbose ext
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.align 5
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NESTED(handle_\exception, PT_SIZE, sp)
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.set noat
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SAVE_ALL
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FEXPORT(handle_\exception\ext)
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__BUILD_clear_\clear
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.set at
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__BUILD_\verbose \exception
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move a0, sp
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PTR_LA ra, ret_from_exception
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j do_\handler
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END(handle_\exception)
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.endm
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.macro BUILD_HANDLER exception handler clear verbose
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__BUILD_HANDLER \exception \handler \clear \verbose _int
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.endm
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BUILD_HANDLER adel ade ade silent /* #4 */
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BUILD_HANDLER ades ade ade silent /* #5 */
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BUILD_HANDLER ibe be cli silent /* #6 */
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BUILD_HANDLER dbe be cli silent /* #7 */
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BUILD_HANDLER bp bp sti silent /* #9 */
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BUILD_HANDLER ri ri sti silent /* #10 */
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BUILD_HANDLER cpu cpu sti silent /* #11 */
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BUILD_HANDLER ov ov sti silent /* #12 */
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BUILD_HANDLER tr tr sti silent /* #13 */
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BUILD_HANDLER fpe fpe fpe silent /* #15 */
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BUILD_HANDLER mdmx mdmx sti silent /* #22 */
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BUILD_HANDLER watch watch sti verbose /* #23 */
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BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
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BUILD_HANDLER mt mt sti silent /* #25 */
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BUILD_HANDLER dsp dsp sti silent /* #26 */
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BUILD_HANDLER reserved reserved sti verbose /* others */
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.align 5
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LEAF(handle_ri_rdhwr_vivt)
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#ifdef CONFIG_MIPS_MT_SMTC
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PANIC_PIC("handle_ri_rdhwr_vivt called")
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#else
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.set push
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.set noat
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.set noreorder
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/* check if TLB contains a entry for EPC */
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MFC0 k1, CP0_ENTRYHI
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andi k1, 0xff /* ASID_MASK */
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MFC0 k0, CP0_EPC
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PTR_SRL k0, PAGE_SHIFT + 1
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PTR_SLL k0, PAGE_SHIFT + 1
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or k1, k0
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MTC0 k1, CP0_ENTRYHI
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mtc0_tlbw_hazard
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tlbp
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tlb_probe_hazard
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mfc0 k1, CP0_INDEX
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.set pop
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bltz k1, handle_ri /* slow path */
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/* fall thru */
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#endif
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END(handle_ri_rdhwr_vivt)
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LEAF(handle_ri_rdhwr)
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.set push
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.set noat
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.set noreorder
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/* 0x7c03e83b: rdhwr v1,$29 */
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MFC0 k1, CP0_EPC
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lui k0, 0x7c03
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lw k1, (k1)
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ori k0, 0xe83b
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.set reorder
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bne k0, k1, handle_ri /* if not ours */
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/* The insn is rdhwr. No need to check CAUSE.BD here. */
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get_saved_sp /* k1 := current_thread_info */
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.set noreorder
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MFC0 k0, CP0_EPC
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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ori k1, _THREAD_MASK
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xori k1, _THREAD_MASK
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LONG_L v1, TI_TP_VALUE(k1)
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LONG_ADDIU k0, 4
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jr k0
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rfe
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#else
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#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
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LONG_ADDIU k0, 4 /* stall on $k0 */
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#else
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.set at=v1
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LONG_ADDIU k0, 4
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.set noat
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#endif
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MTC0 k0, CP0_EPC
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/* I hope three instructions between MTC0 and ERET are enough... */
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ori k1, _THREAD_MASK
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xori k1, _THREAD_MASK
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LONG_L v1, TI_TP_VALUE(k1)
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.set mips3
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eret
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.set mips0
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#endif
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.set pop
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END(handle_ri_rdhwr)
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#ifdef CONFIG_64BIT
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/* A temporary overflow handler used by check_daddi(). */
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__INIT
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BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */
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#endif
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