120db2cba8
Patch from Tony Lindgren Update misc OMAP core code from linux-omap tree: - McBSP updates by Samuel Ortiz, Andrzej Zaborowski - Whitespace cleanups by Ladislav Michl - Other fixes by various linux-omap developers Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
246 lines
6.9 KiB
C
246 lines
6.9 KiB
C
/*
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* linux/arch/arm/mach-omap1/irq.c
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*
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* Interrupt handler for all OMAP boards
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*
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* Copyright (C) 2004 Nokia Corporation
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* Written by Tony Lindgren <tony@atomide.com>
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* Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
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*
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* Completely re-written to support various OMAP chips with bank specific
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* interrupt handlers.
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*
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* Some snippets of the code taken from the older OMAP interrupt handler
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* Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
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*
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* GPIO interrupt handler moved to gpio.c by Juha Yrjola
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/cpu.h>
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#include <asm/io.h>
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#define IRQ_BANK(irq) ((irq) >> 5)
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#define IRQ_BIT(irq) ((irq) & 0x1f)
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struct omap_irq_bank {
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unsigned long base_reg;
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unsigned long trigger_map;
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unsigned long wake_enable;
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};
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static unsigned int irq_bank_count;
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static struct omap_irq_bank *irq_banks;
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static inline unsigned int irq_bank_readl(int bank, int offset)
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{
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return omap_readl(irq_banks[bank].base_reg + offset);
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}
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static inline void irq_bank_writel(unsigned long value, int bank, int offset)
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{
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omap_writel(value, irq_banks[bank].base_reg + offset);
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}
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static void omap_ack_irq(unsigned int irq)
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{
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if (irq > 31)
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omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
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omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
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}
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static void omap_mask_irq(unsigned int irq)
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{
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int bank = IRQ_BANK(irq);
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u32 l;
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l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
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l |= 1 << IRQ_BIT(irq);
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omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
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}
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static void omap_unmask_irq(unsigned int irq)
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{
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int bank = IRQ_BANK(irq);
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u32 l;
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l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
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l &= ~(1 << IRQ_BIT(irq));
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omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
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}
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static void omap_mask_ack_irq(unsigned int irq)
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{
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omap_mask_irq(irq);
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omap_ack_irq(irq);
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}
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static int omap_wake_irq(unsigned int irq, unsigned int enable)
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{
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int bank = IRQ_BANK(irq);
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if (enable)
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irq_banks[bank].wake_enable |= IRQ_BIT(irq);
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else
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irq_banks[bank].wake_enable &= ~IRQ_BIT(irq);
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return 0;
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}
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/*
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* Allows tuning the IRQ type and priority
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*
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* NOTE: There is currently no OMAP fiq handler for Linux. Read the
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* mailing list threads on FIQ handlers if you are planning to
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* add a FIQ handler for OMAP.
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*/
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static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
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{
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signed int bank;
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unsigned long val, offset;
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bank = IRQ_BANK(irq);
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/* FIQ is only available on bank 0 interrupts */
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fiq = bank ? 0 : (fiq & 0x1);
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val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
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offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
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irq_bank_writel(val, bank, offset);
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}
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#ifdef CONFIG_ARCH_OMAP730
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static struct omap_irq_bank omap730_irq_banks[] = {
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{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
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{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
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{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
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};
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#endif
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#ifdef CONFIG_ARCH_OMAP15XX
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static struct omap_irq_bank omap1510_irq_banks[] = {
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{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
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{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
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};
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static struct omap_irq_bank omap310_irq_banks[] = {
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{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
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{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
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};
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#endif
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#if defined(CONFIG_ARCH_OMAP16XX)
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static struct omap_irq_bank omap1610_irq_banks[] = {
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{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
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{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
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{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
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{ .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
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};
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#endif
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static struct irqchip omap_irq_chip = {
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.ack = omap_mask_ack_irq,
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.mask = omap_mask_irq,
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.unmask = omap_unmask_irq,
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.set_wake = omap_wake_irq,
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};
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void __init omap_init_irq(void)
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{
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int i, j;
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#ifdef CONFIG_ARCH_OMAP730
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if (cpu_is_omap730()) {
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irq_banks = omap730_irq_banks;
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irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
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}
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#endif
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#ifdef CONFIG_ARCH_OMAP15XX
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if (cpu_is_omap1510()) {
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irq_banks = omap1510_irq_banks;
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irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
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}
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if (cpu_is_omap310()) {
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irq_banks = omap310_irq_banks;
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irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
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}
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#endif
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#if defined(CONFIG_ARCH_OMAP16XX)
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if (cpu_is_omap16xx()) {
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irq_banks = omap1610_irq_banks;
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irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
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}
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#endif
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printk("Total of %i interrupts in %i interrupt banks\n",
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irq_bank_count * 32, irq_bank_count);
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/* Mask and clear all interrupts */
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for (i = 0; i < irq_bank_count; i++) {
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irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
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irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
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}
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/* Clear any pending interrupts */
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irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
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irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
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/* Enable interrupts in global mask */
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if (cpu_is_omap730()) {
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irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
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}
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/* Install the interrupt handlers for each bank */
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for (i = 0; i < irq_bank_count; i++) {
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for (j = i * 32; j < (i + 1) * 32; j++) {
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int irq_trigger;
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irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
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omap_irq_set_cfg(j, 0, 0, irq_trigger);
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set_irq_chip(j, &omap_irq_chip);
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set_irq_handler(j, do_level_IRQ);
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set_irq_flags(j, IRQF_VALID);
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}
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}
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/* Unmask level 2 handler */
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if (cpu_is_omap730())
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omap_unmask_irq(INT_730_IH2_IRQ);
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else if (cpu_is_omap1510())
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omap_unmask_irq(INT_1510_IH2_IRQ);
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else if (cpu_is_omap16xx())
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omap_unmask_irq(INT_1610_IH2_IRQ);
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}
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