ec298edf02
-----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEZH8oZUiU471FcZm+ONu9yGCSaT4FAmFVcNQACgkQONu9yGCS aT538BAAx7oC+ow1nwmCSj3J9B9B+3IykXJs22VqZOSWZcI9+OaUzqa+67vn136w c2MGkMIkmQEhgsnLCWgOlfV2PFNIX/yVPXGT2Df2Io4fTpfkXXKZTA+PWCi8F7FI AiVT6A2QqiZsuQnoe1Rgyx1UHqDhZ4ptwK+uNMpccvtiSp6yhb9coOvfdDsWPdjE 9YUPN2rLpBfq9UGxii66NBxQAJpYAPRSgbQXmTj3UNF7KNOmLZbGWbJC5DybZiQB VK4Bgz5OcIfH6gnTy+bIYn3sIrb4I2WML51gtLZcT6QoiCGYFNML6LChpk9oJ7sl iXXYGRheek0hnsKaObPyIulqBcZXjsKmYeuohlHnFB0p7j3NAJ4LTg2lCAEeQjDR 6JgMOhuTEfyes+ciK75m0GWzPUs+/FnGP+CGXVCeEwT7bW8rNPZSIfsb6GTgJDXn OE3N/FsaL9qa7XbFEIprPmVa5A2SOIUc4PCnuhckLIIhZrTASktCt1vt1Rl8D50F dGXZQ0Vor279NeqnkMySycSaTV6HPD7n+dOMXRXpdWmTYN/7kAxSLD4thFZcyG7s Ms2dzTt7C/gHcdpfE2qHVBCBYMowOuisuZwWrb451Y2ks1shk88zRHMt8ydNrWvq GNGOpSFlcS+7umPzQ9CfA5k+3NFTYMVkVv2Vp/9J1nQYsi3OByc= =r8NE -----END PGP SIGNATURE----- Merge 5.4.150 into android11-5.4-lts Changes in 5.4.150 ocfs2: drop acl cache for directories too usb: gadget: r8a66597: fix a loop in set_feature() usb: dwc2: gadget: Fix ISOC flow for BDMA and Slave usb: dwc2: gadget: Fix ISOC transfer complete handling for DDMA usb: musb: tusb6010: uninitialized data in tusb_fifo_write_unaligned() cifs: fix incorrect check for null pointer in header_assemble xen/x86: fix PV trap handling on secondary processors usb-storage: Add quirk for ScanLogic SL11R-IDE older than 2.6c USB: serial: cp210x: add ID for GW Instek GDM-834x Digital Multimeter USB: cdc-acm: fix minor-number release binder: make sure fd closes complete staging: greybus: uart: fix tty use after free Re-enable UAS for LaCie Rugged USB3-FW with fk quirk usb: core: hcd: Add support for deferring roothub registration USB: serial: mos7840: remove duplicated 0xac24 device ID USB: serial: option: add Telit LN920 compositions USB: serial: option: remove duplicate USB device ID USB: serial: option: add device id for Foxconn T99W265 mcb: fix error handling in mcb_alloc_bus() erofs: fix up erofs_lookup tracepoint btrfs: prevent __btrfs_dump_space_info() to underflow its free space xhci: Set HCD flag to defer primary roothub registration serial: mvebu-uart: fix driver's tx_empty callback net: hso: fix muxed tty registration afs: Fix incorrect triggering of sillyrename on 3rd-party invalidation platform/x86/intel: punit_ipc: Drop wrong use of ACPI_PTR() enetc: Fix illegal access when reading affinity_hint bnxt_en: Fix TX timeout when TX ring size is set to the smallest net/smc: add missing error check in smc_clc_prfx_set() gpio: uniphier: Fix void functions to remove return value qed: rdma - don't wait for resources under hw error recovery flow net/mlx4_en: Don't allow aRFS for encapsulated packets scsi: iscsi: Adjust iface sysfs attr detection tty: synclink_gt, drop unneeded forward declarations tty: synclink_gt: rename a conflicting function name fpga: machxo2-spi: Return an error on failure fpga: machxo2-spi: Fix missing error code in machxo2_write_complete() thermal/core: Potential buffer overflow in thermal_build_list_of_policies() cifs: fix a sign extension bug scsi: qla2xxx: Restore initiator in dual mode scsi: lpfc: Use correct scnprintf() limit irqchip/goldfish-pic: Select GENERIC_IRQ_CHIP to fix build irqchip/gic-v3-its: Fix potential VPE leak on error md: fix a lock order reversal in md_alloc blktrace: Fix uaf in blk_trace access after removing by sysfs net: macb: fix use after free on rmmod net: stmmac: allow CSR clock of 300MHz m68k: Double cast io functions to unsigned long ipv6: delay fib6_sernum increase in fib6_add bpf: Add oversize check before call kvcalloc() xen/balloon: use a kernel thread instead a workqueue nvme-multipath: fix ANA state updates when a namespace is not present sparc32: page align size in arch_dma_alloc blk-cgroup: fix UAF by grabbing blkcg lock before destroying blkg pd compiler.h: Introduce absolute_pointer macro net: i825xx: Use absolute_pointer for memcpy from fixed memory location sparc: avoid stringop-overread errors qnx4: avoid stringop-overread errors parisc: Use absolute_pointer() to define PAGE0 arm64: Mark __stack_chk_guard as __ro_after_init alpha: Declare virt_to_phys and virt_to_bus parameter as pointer to volatile net: 6pack: Fix tx timeout and slot time spi: Fix tegra20 build with CONFIG_PM=n EDAC/synopsys: Fix wrong value type assignment for edac_mode thermal/drivers/int340x: Do not set a wrong tcc offset on resume arm64: dts: marvell: armada-37xx: Extend PCIe MEM space xen/balloon: fix balloon kthread freezing qnx4: work around gcc false positive warning bug Linux 5.4.150 Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: I779eab319e88381a228b9956ce1d2d45d76f2d2c
500 lines
10 KiB
Plaintext
500 lines
10 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menu "IRQ chip support"
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config IRQCHIP
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def_bool y
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depends on OF_IRQ
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config ARM_GIC
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bool
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_IRQ_MULTI_HANDLER
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config ARM_GIC_PM
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bool
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depends on PM
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select ARM_GIC
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config ARM_GIC_MAX_NR
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int
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depends on ARM_GIC
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default 2 if ARCH_REALVIEW
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default 1
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config ARM_GIC_V2M
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bool
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depends on PCI
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select ARM_GIC
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select PCI_MSI
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config GIC_NON_BANKED
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bool
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config ARM_GIC_V3
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bool
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select GENERIC_IRQ_MULTI_HANDLER
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select IRQ_DOMAIN_HIERARCHY
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select PARTITION_PERCPU
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config ARM_GIC_V3_ITS
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bool
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select GENERIC_MSI_IRQ_DOMAIN
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default ARM_GIC_V3
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config ARM_GIC_V3_ITS_PCI
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bool
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depends on ARM_GIC_V3_ITS
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depends on PCI
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depends on PCI_MSI
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default ARM_GIC_V3_ITS
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config ARM_GIC_V3_ITS_FSL_MC
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bool
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depends on ARM_GIC_V3_ITS
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depends on FSL_MC_BUS
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default ARM_GIC_V3_ITS
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config ARM_NVIC
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bool
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_IRQ_CHIP
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config ARM_VIC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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config ARM_VIC_NR
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int
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default 4 if ARCH_S5PV210
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default 2
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depends on ARM_VIC
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help
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The maximum number of VICs available in the system, for
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power management.
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config ARMADA_370_XP_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select PCI_MSI if PCI
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config ALPINE_MSI
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bool
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depends on PCI
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select PCI_MSI
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select GENERIC_IRQ_CHIP
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config AL_FIC
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bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
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depends on OF || COMPILE_TEST
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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help
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Support Amazon's Annapurna Labs Fabric Interrupt Controller.
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config ATMEL_AIC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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select SPARSE_IRQ
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config ATMEL_AIC5_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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select SPARSE_IRQ
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config I8259
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bool
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select IRQ_DOMAIN
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config BCM6345_L1_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config BCM7038_L1_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config BCM7120_L2_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config BRCMSTB_L2_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DAVINCI_AINTC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DAVINCI_CP_INTC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config DW_APB_ICTL
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config FARADAY_FTINTC010
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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select SPARSE_IRQ
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config HISILICON_IRQ_MBIGEN
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bool
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select ARM_GIC_V3
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select ARM_GIC_V3_ITS
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config IMGPDC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config IXP4XX_IRQ
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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select SPARSE_IRQ
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config MADERA_IRQ
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tristate
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config IRQ_MIPS_CPU
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bool
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select GENERIC_IRQ_CHIP
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select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
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select IRQ_DOMAIN
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select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config CLPS711X_IRQCHIP
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bool
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depends on ARCH_CLPS711X
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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select SPARSE_IRQ
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default y
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config OMPIC
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bool
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config OR1K_PIC
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bool
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select IRQ_DOMAIN
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config OMAP_IRQCHIP
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config ORION_IRQCHIP
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_MULTI_HANDLER
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config PIC32_EVIC
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config JCORE_AIC
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bool "J-Core integrated AIC" if COMPILE_TEST
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depends on OF
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select IRQ_DOMAIN
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help
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Support for the J-Core integrated AIC.
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config RDA_INTC
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bool
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select IRQ_DOMAIN
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config RENESAS_INTC_IRQPIN
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bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
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select IRQ_DOMAIN
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help
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Enable support for the Renesas Interrupt Controller for external
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interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
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config RENESAS_IRQC
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bool "Renesas R-Mobile APE6 and R-Car IRQC support" if COMPILE_TEST
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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help
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Enable support for the Renesas Interrupt Controller for external
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devices, as found on R-Mobile APE6, R-Car Gen2, and R-Car Gen3 SoCs.
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config RENESAS_RZA1_IRQC
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bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
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select IRQ_DOMAIN_HIERARCHY
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help
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Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
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to 8 external interrupts with configurable sense select.
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config ST_IRQCHIP
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bool
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select REGMAP
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select MFD_SYSCON
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help
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Enables SysCfg Controlled IRQs on STi based platforms.
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config TANGO_IRQ
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config TB10X_IRQC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config TS4800_IRQ
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tristate "TS-4800 IRQ controller"
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select IRQ_DOMAIN
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depends on HAS_IOMEM
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depends on SOC_IMX51 || COMPILE_TEST
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help
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Support for the TS-4800 FPGA IRQ controller
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config VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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config VERSATILE_FPGA_IRQ_NR
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int
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default 4
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depends on VERSATILE_FPGA_IRQ
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config XTENSA_MX
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_EFFECTIVE_AFF_MASK
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config XILINX_INTC
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bool
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select IRQ_DOMAIN
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config IRQ_CROSSBAR
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bool
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help
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Support for a CROSSBAR ip that precedes the main interrupt controller.
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The primary irqchip invokes the crossbar's callback which inturn allocates
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a free irq and configures the IP. Thus the peripheral interrupts are
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routed to one of the free irqchip interrupt lines.
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config KEYSTONE_IRQ
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tristate "Keystone 2 IRQ controller IP"
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depends on ARCH_KEYSTONE
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help
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Support for Texas Instruments Keystone 2 IRQ controller IP which
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is part of the Keystone 2 IPC mechanism
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config MIPS_GIC
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bool
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select GENERIC_IRQ_IPI
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select IRQ_DOMAIN_HIERARCHY
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select MIPS_CM
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config INGENIC_IRQ
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bool
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depends on MACH_INGENIC
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default y
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config INGENIC_TCU_IRQ
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bool "Ingenic JZ47xx TCU interrupt controller"
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default MACH_INGENIC
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depends on MIPS || COMPILE_TEST
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select MFD_SYSCON
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select GENERIC_IRQ_CHIP
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help
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Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
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JZ47xx SoCs.
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If unsure, say N.
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config RENESAS_H8300H_INTC
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bool
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select IRQ_DOMAIN
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config RENESAS_H8S_INTC
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bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
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select IRQ_DOMAIN
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help
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Enable support for the Renesas H8/300 Interrupt Controller, as found
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on Renesas H8S SoCs.
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config IMX_GPCV2
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bool
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select IRQ_DOMAIN
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help
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Enables the wakeup IRQs for IMX platforms with GPCv2 block
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config IRQ_MXS
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def_bool y if MACH_ASM9260 || ARCH_MXS
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select IRQ_DOMAIN
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select STMP_DEVICE
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config MSCC_OCELOT_IRQ
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config MVEBU_GICP
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bool
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config MVEBU_ICU
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bool
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config MVEBU_ODMI
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bool
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select GENERIC_MSI_IRQ_DOMAIN
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config MVEBU_PIC
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bool
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config MVEBU_SEI
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bool
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config LS_SCFG_MSI
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def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
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depends on PCI && PCI_MSI
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config PARTITION_PERCPU
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bool
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config EZNPS_GIC
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bool "NPS400 Global Interrupt Manager (GIM)"
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depends on ARC || (COMPILE_TEST && !64BIT)
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select IRQ_DOMAIN
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help
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Support the EZchip NPS400 global interrupt controller
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config STM32_EXTI
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config QCOM_IRQ_COMBINER
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bool "QCOM IRQ combiner support"
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depends on ARCH_QCOM && ACPI
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select IRQ_DOMAIN_HIERARCHY
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help
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Say yes here to add support for the IRQ combiner devices embedded
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in Qualcomm Technologies chips.
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config IRQ_UNIPHIER_AIDET
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bool "UniPhier AIDET support" if COMPILE_TEST
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depends on ARCH_UNIPHIER || COMPILE_TEST
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default ARCH_UNIPHIER
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select IRQ_DOMAIN_HIERARCHY
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help
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Support for the UniPhier AIDET (ARM Interrupt Detector).
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config MESON_IRQ_GPIO
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bool "Meson GPIO Interrupt Multiplexer"
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depends on ARCH_MESON
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select IRQ_DOMAIN_HIERARCHY
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help
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Support Meson SoC Family GPIO Interrupt Multiplexer
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config GOLDFISH_PIC
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bool "Goldfish programmable interrupt controller"
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depends on MIPS && (GOLDFISH || COMPILE_TEST)
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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help
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Say yes here to enable Goldfish interrupt controller driver used
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for Goldfish based virtual platforms.
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config QCOM_PDC
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tristate "QCOM PDC"
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depends on ARCH_QCOM
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select IRQ_DOMAIN_HIERARCHY
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help
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Power Domain Controller driver to manage and configure wakeup
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IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
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config CSKY_MPINTC
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bool "C-SKY Multi Processor Interrupt Controller"
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depends on CSKY
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help
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Say yes here to enable C-SKY SMP interrupt controller driver used
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for C-SKY SMP system.
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In fact it's not mmio map in hw and it use ld/st to visit the
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controller's register inside CPU.
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config CSKY_APB_INTC
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bool "C-SKY APB Interrupt Controller"
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depends on CSKY
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help
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Say yes here to enable C-SKY APB interrupt controller driver used
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by C-SKY single core SOC system. It use mmio map apb-bus to visit
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the controller's register.
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config IMX_IRQSTEER
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bool "i.MX IRQSTEER support"
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depends on ARCH_MXC || COMPILE_TEST
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default ARCH_MXC
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select IRQ_DOMAIN
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help
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Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
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config LS1X_IRQ
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bool "Loongson-1 Interrupt Controller"
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depends on MACH_LOONGSON32
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default y
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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help
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Support for the Loongson-1 platform Interrupt Controller.
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config TI_SCI_INTR_IRQCHIP
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bool
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depends on TI_SCI_PROTOCOL
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select IRQ_DOMAIN_HIERARCHY
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help
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This enables the irqchip driver support for K3 Interrupt router
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over TI System Control Interface available on some new TI's SoCs.
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If you wish to use interrupt router irq resources managed by the
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TI System Controller, say Y here. Otherwise, say N.
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config TI_SCI_INTA_IRQCHIP
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bool
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depends on TI_SCI_PROTOCOL
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select IRQ_DOMAIN_HIERARCHY
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select TI_SCI_INTA_MSI_DOMAIN
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help
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This enables the irqchip driver support for K3 Interrupt aggregator
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over TI System Control Interface available on some new TI's SoCs.
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If you wish to use interrupt aggregator irq resources managed by the
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TI System Controller, say Y here. Otherwise, say N.
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config SIFIVE_PLIC
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bool "SiFive Platform-Level Interrupt Controller"
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depends on RISCV
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help
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|
This enables support for the PLIC chip found in SiFive (and
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potentially other) RISC-V systems. The PLIC controls devices
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interrupts and connects them to each core's local interrupt
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controller. Aside from timer and software interrupts, all other
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interrupt sources are subordinate to the PLIC.
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If you don't know what to do here, say Y.
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endmenu
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