6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
360 lines
8.5 KiB
C
360 lines
8.5 KiB
C
/*
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* ATI Frame Buffer Device Driver Core Definitions
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*/
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#include <linux/spinlock.h>
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#include <linux/wait.h>
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/*
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* Elements of the hardware specific atyfb_par structure
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*/
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struct crtc {
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u32 vxres;
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u32 vyres;
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u32 xoffset;
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u32 yoffset;
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u32 bpp;
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u32 h_tot_disp;
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u32 h_sync_strt_wid;
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u32 v_tot_disp;
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u32 v_sync_strt_wid;
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u32 vline_crnt_vline;
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u32 off_pitch;
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u32 gen_cntl;
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u32 dp_pix_width; /* acceleration */
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u32 dp_chain_mask; /* acceleration */
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#ifdef CONFIG_FB_ATY_GENERIC_LCD
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u32 horz_stretching;
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u32 vert_stretching;
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u32 ext_vert_stretch;
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u32 shadow_h_tot_disp;
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u32 shadow_h_sync_strt_wid;
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u32 shadow_v_tot_disp;
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u32 shadow_v_sync_strt_wid;
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u32 lcd_gen_cntl;
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u32 lcd_config_panel;
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u32 lcd_index;
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#endif
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};
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struct aty_interrupt {
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wait_queue_head_t wait;
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unsigned int count;
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int pan_display;
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};
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struct pll_info {
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int pll_max;
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int pll_min;
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int sclk, mclk, mclk_pm, xclk;
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int ref_div;
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int ref_clk;
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int ecp_max;
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};
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typedef struct {
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u16 unknown1;
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u16 PCLK_min_freq;
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u16 PCLK_max_freq;
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u16 unknown2;
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u16 ref_freq;
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u16 ref_divider;
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u16 unknown3;
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u16 MCLK_pwd;
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u16 MCLK_max_freq;
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u16 XCLK_max_freq;
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u16 SCLK_freq;
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} __attribute__ ((packed)) PLL_BLOCK_MACH64;
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struct pll_514 {
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u8 m;
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u8 n;
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};
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struct pll_18818 {
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u32 program_bits;
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u32 locationAddr;
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u32 period_in_ps;
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u32 post_divider;
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};
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struct pll_ct {
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u8 pll_ref_div;
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u8 pll_gen_cntl;
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u8 mclk_fb_div;
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u8 mclk_fb_mult; /* 2 ro 4 */
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u8 sclk_fb_div;
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u8 pll_vclk_cntl;
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u8 vclk_post_div;
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u8 vclk_fb_div;
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u8 pll_ext_cntl;
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u8 ext_vpll_cntl;
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u8 spll_cntl2;
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u32 dsp_config; /* Mach64 GTB DSP */
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u32 dsp_on_off; /* Mach64 GTB DSP */
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u32 dsp_loop_latency;
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u32 fifo_size;
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u32 xclkpagefaultdelay;
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u32 xclkmaxrasdelay;
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u8 xclk_ref_div;
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u8 xclk_post_div;
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u8 mclk_post_div_real;
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u8 xclk_post_div_real;
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u8 vclk_post_div_real;
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u8 features;
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#ifdef CONFIG_FB_ATY_GENERIC_LCD
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u32 xres; /* use for LCD stretching/scaling */
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#endif
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};
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/*
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for pll_ct.features
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*/
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#define DONT_USE_SPLL 0x1
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#define DONT_USE_XDLL 0x2
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#define USE_CPUCLK 0x4
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#define POWERDOWN_PLL 0x8
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union aty_pll {
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struct pll_ct ct;
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struct pll_514 ibm514;
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struct pll_18818 ics2595;
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};
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/*
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* The hardware parameters for each card
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*/
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struct atyfb_par {
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struct aty_cmap_regs __iomem *aty_cmap_regs;
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struct { u8 red, green, blue; } palette[256];
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const struct aty_dac_ops *dac_ops;
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const struct aty_pll_ops *pll_ops;
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void __iomem *ati_regbase;
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unsigned long clk_wr_offset; /* meaning overloaded, clock id by CT */
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struct crtc crtc;
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union aty_pll pll;
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struct pll_info pll_limits;
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u32 features;
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u32 ref_clk_per;
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u32 pll_per;
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u32 mclk_per;
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u32 xclk_per;
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u8 bus_type;
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u8 ram_type;
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u8 mem_refresh_rate;
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u16 pci_id;
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u32 accel_flags;
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int blitter_may_be_busy;
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int asleep;
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int lock_blank;
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unsigned long res_start;
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unsigned long res_size;
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struct pci_dev *pdev;
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#ifdef __sparc__
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struct pci_mmap_map *mmap_map;
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u8 mmaped;
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#endif
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int open;
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#ifdef CONFIG_FB_ATY_GENERIC_LCD
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unsigned long bios_base_phys;
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unsigned long bios_base;
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unsigned long lcd_table;
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u16 lcd_width;
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u16 lcd_height;
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u32 lcd_pixclock;
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u16 lcd_refreshrate;
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u16 lcd_htotal;
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u16 lcd_hdisp;
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u16 lcd_hsync_dly;
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u16 lcd_hsync_len;
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u16 lcd_vtotal;
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u16 lcd_vdisp;
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u16 lcd_vsync_len;
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u16 lcd_right_margin;
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u16 lcd_lower_margin;
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u16 lcd_hblank_len;
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u16 lcd_vblank_len;
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#endif
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unsigned long aux_start; /* auxiliary aperture */
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unsigned long aux_size;
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struct aty_interrupt vblank;
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unsigned long irq_flags;
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unsigned int irq;
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spinlock_t int_lock;
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#ifdef CONFIG_MTRR
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int mtrr_aper;
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int mtrr_reg;
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#endif
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};
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/*
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* ATI Mach64 features
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*/
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#define M64_HAS(feature) ((par)->features & (M64F_##feature))
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#define M64F_RESET_3D 0x00000001
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#define M64F_MAGIC_FIFO 0x00000002
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#define M64F_GTB_DSP 0x00000004
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#define M64F_FIFO_32 0x00000008
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#define M64F_SDRAM_MAGIC_PLL 0x00000010
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#define M64F_MAGIC_POSTDIV 0x00000020
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#define M64F_INTEGRATED 0x00000040
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#define M64F_CT_BUS 0x00000080
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#define M64F_VT_BUS 0x00000100
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#define M64F_MOBIL_BUS 0x00000200
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#define M64F_GX 0x00000400
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#define M64F_CT 0x00000800
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#define M64F_VT 0x00001000
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#define M64F_GT 0x00002000
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#define M64F_MAGIC_VRAM_SIZE 0x00004000
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#define M64F_G3_PB_1_1 0x00008000
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#define M64F_G3_PB_1024x768 0x00010000
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#define M64F_EXTRA_BRIGHT 0x00020000
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#define M64F_LT_LCD_REGS 0x00040000
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#define M64F_XL_DLL 0x00080000
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#define M64F_MFB_FORCE_4 0x00100000
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#define M64F_HW_TRIPLE 0x00200000
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/*
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* Register access
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*/
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static inline u32 aty_ld_le32(int regindex, const struct atyfb_par *par)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef CONFIG_ATARI
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return in_le32((volatile u32 *)(par->ati_regbase + regindex));
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#else
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return readl(par->ati_regbase + regindex);
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#endif
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}
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static inline void aty_st_le32(int regindex, u32 val, const struct atyfb_par *par)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef CONFIG_ATARI
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out_le32((volatile u32 *)(par->ati_regbase + regindex), val);
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#else
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writel(val, par->ati_regbase + regindex);
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#endif
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}
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static inline void aty_st_le16(int regindex, u16 val,
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const struct atyfb_par *par)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef CONFIG_ATARI
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out_le16((volatile u16 *)(par->ati_regbase + regindex), val);
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#else
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writel(val, par->ati_regbase + regindex);
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#endif
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}
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static inline u8 aty_ld_8(int regindex, const struct atyfb_par *par)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef CONFIG_ATARI
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return in_8(par->ati_regbase + regindex);
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#else
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return readb(par->ati_regbase + regindex);
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#endif
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}
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static inline void aty_st_8(int regindex, u8 val, const struct atyfb_par *par)
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{
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/* Hack for bloc 1, should be cleanly optimized by compiler */
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if (regindex >= 0x400)
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regindex -= 0x800;
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#ifdef CONFIG_ATARI
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out_8(par->ati_regbase + regindex, val);
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#else
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writeb(val, par->ati_regbase + regindex);
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#endif
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}
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#if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
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extern void aty_st_lcd(int index, u32 val, const struct atyfb_par *par);
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extern u32 aty_ld_lcd(int index, const struct atyfb_par *par);
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#endif
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/*
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* DAC operations
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*/
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struct aty_dac_ops {
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int (*set_dac) (const struct fb_info * info,
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const union aty_pll * pll, u32 bpp, u32 accel);
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};
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extern const struct aty_dac_ops aty_dac_ibm514; /* IBM RGB514 */
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extern const struct aty_dac_ops aty_dac_ati68860b; /* ATI 68860-B */
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extern const struct aty_dac_ops aty_dac_att21c498; /* AT&T 21C498 */
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extern const struct aty_dac_ops aty_dac_unsupported; /* unsupported */
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extern const struct aty_dac_ops aty_dac_ct; /* Integrated */
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/*
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* Clock operations
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*/
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struct aty_pll_ops {
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int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
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u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
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void (*set_pll) (const struct fb_info * info, const union aty_pll * pll);
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void (*get_pll) (const struct fb_info *info, union aty_pll * pll);
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int (*init_pll) (const struct fb_info * info, union aty_pll * pll);
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};
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extern const struct aty_pll_ops aty_pll_ati18818_1; /* ATI 18818 */
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extern const struct aty_pll_ops aty_pll_stg1703; /* STG 1703 */
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extern const struct aty_pll_ops aty_pll_ch8398; /* Chrontel 8398 */
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extern const struct aty_pll_ops aty_pll_att20c408; /* AT&T 20C408 */
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extern const struct aty_pll_ops aty_pll_ibm514; /* IBM RGB514 */
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extern const struct aty_pll_ops aty_pll_unsupported; /* unsupported */
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extern const struct aty_pll_ops aty_pll_ct; /* Integrated */
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extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
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extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);
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/*
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* Hardware cursor support
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*/
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extern int aty_init_cursor(struct fb_info *info);
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/*
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* Hardware acceleration
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*/
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static inline void wait_for_fifo(u16 entries, const struct atyfb_par *par)
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{
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while ((aty_ld_le32(FIFO_STAT, par) & 0xffff) >
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((u32) (0x8000 >> entries)));
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}
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static inline void wait_for_idle(struct atyfb_par *par)
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{
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wait_for_fifo(16, par);
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while ((aty_ld_le32(GUI_STAT, par) & 1) != 0);
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par->blitter_may_be_busy = 0;
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}
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extern void aty_reset_engine(const struct atyfb_par *par);
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extern void aty_init_engine(struct atyfb_par *par, struct fb_info *info);
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extern void aty_st_pll_ct(int offset, u8 val, const struct atyfb_par *par);
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extern u8 aty_ld_pll_ct(int offset, const struct atyfb_par *par);
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