Han Xu d417d5eb29 clk: imx: imx6sx: remove the SET_RATE_PARENT flag for QSPI clocks ... [ Upstream commit b1ff1bfe81e763420afd5f3f25f0b3cbfd97055c ] There is no dedicate parent clock for QSPI so SET_RATE_PARENT flag should not be used. For instance, the default parent clock for QSPI is pll2_bus, which is also the parent clock for quite a few modules, such as MMDC, once GPMI NAND set clock rate for EDO5 mode can cause system hang due to pll2_bus rate changed. Fixes: f1541e15e3 ("clk: imx6sx: Switch to clk_hw based API") Signed-off-by: Han Xu <han.xu@nxp.com> Link: https://lore.kernel.org/r/20220915150959.3646702-1-han.xu@nxp.com Tested-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2022-10-05 10:37:45 +02:00
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clk-busy.c
clk-composite-7ulp.c
clk-composite-8m.c
clk-cpu.c
clk-divider-gate.c
clk-fixup-div.c
clk-fixup-mux.c
clk-frac-pll.c
clk-gate2.c
clk-gate-exclusive.c
clk-imx1.c
clk-imx5.c
clk-imx6q.c
clk-imx6sl.c
clk-imx6sll.c
clk-imx6sx.c	clk: imx: imx6sx: remove the SET_RATE_PARENT flag for QSPI clocks	2022-10-05 10:37:45 +02:00
clk-imx6ul.c
clk-imx7d.c	clk: imx7d: Remove audio_mclk_root_clk	2022-04-15 14:18:18 +02:00
clk-imx7ulp.c
clk-imx8mm.c
clk-imx8mn.c
clk-imx8mq.c
clk-imx8qxp-lpcg.c
clk-imx8qxp-lpcg.h
clk-imx8qxp.c
clk-imx21.c
clk-imx25.c
clk-imx27.c
clk-imx31.c
clk-imx35.c
clk-lpcg-scu.c
clk-pfd.c
clk-pfdv2.c
clk-pll14xx.c
clk-pllv1.c
clk-pllv2.c
clk-pllv3.c
clk-pllv4.c
clk-sccg-pll.c
clk-scu.c
clk-scu.h
clk-vf610.c
clk.c
clk.h
Kconfig
Makefile